OV - exec - Function main._omp

	Function: main._omp_fn.4	Module: exec	Source: stream.c:330-332	Coverage (incl. loops): 94.85% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c: 330 - 332

--------------------------------------------------------------------------------

330: #pragma omp parallel for

331: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

332: 	    b[j] = scalar*c[j];

0x401a60 PUSH	%RBP

0x401a61 MOV	$0x401060,%RAX

0x401a6b MOV	%RSP,%RBP

0x401a6e PUSH	%R12

0x401a70 PUSH	%RBX

0x401a71 MOV	%RDI,%RBX

0x401a74 CALL	%RAX

0x401a76 MOVSXD	%EAX,%R12

0x401a79 MOV	$0x401030,%RAX

0x401a83 CALL	%RAX

0x401a85 MOVSXD	%EAX,%RCX

0x401a88 MOV	$0x33450000,%EAX

0x401a8d CQTO

0x401a8f IDIV	%R12

0x401a92 CMP	%RDX,%RCX

0x401a95 JL	401be0

0x401a9b IMUL	%RAX,%RCX

0x401a9f ADD	%RCX,%RDX

0x401aa2 ADD	%RDX,%RAX

0x401aa5 CMP	%RAX,%RDX

0x401aa8 JGE	401bcf

0x401aae MOV	%RAX,%RDI

0x401ab1 MOV	$0x19a6860e0,%R8

0x401abb MOV	$0x4060e0,%RSI

0x401ac5 VMOVSD	(%RBX),%XMM0

0x401ac9 SUB	%RDX,%RDI

0x401acc AND	$0x7,%EDI

0x401acf JE	401b60

0x401ad5 CMP	$0x1,%RDI

0x401ad9 JE	401b4d

0x401adb CMP	$0x2,%RDI

0x401adf JE	401b3f

0x401ae1 CMP	$0x3,%RDI

0x401ae5 JE	401b31

0x401ae7 CMP	$0x4,%RDI

0x401aeb JE	401b23

0x401aed CMP	$0x5,%RDI

0x401af1 JE	401b15

0x401af3 CMP	$0x6,%RDI

0x401af7 JE	401b07

0x401af9 VMULSD	(%RSI,%RDX,8),%XMM0,%XMM1

0x401afe VMOVSD	%XMM1,(%R8,%RDX,8)

0x401b04 INC	%RDX

0x401b07 VMULSD	(%RSI,%RDX,8),%XMM0,%XMM2

0x401b0c VMOVSD	%XMM2,(%R8,%RDX,8)

0x401b12 INC	%RDX

0x401b15 VMULSD	(%RSI,%RDX,8),%XMM0,%XMM3

0x401b1a VMOVSD	%XMM3,(%R8,%RDX,8)

0x401b20 INC	%RDX

0x401b23 VMULSD	(%RSI,%RDX,8),%XMM0,%XMM4

0x401b28 VMOVSD	%XMM4,(%R8,%RDX,8)

0x401b2e INC	%RDX

0x401b31 VMULSD	(%RSI,%RDX,8),%XMM0,%XMM5

0x401b36 VMOVSD	%XMM5,(%R8,%RDX,8)

0x401b3c INC	%RDX

0x401b3f VMULSD	(%RSI,%RDX,8),%XMM0,%XMM6

0x401b44 VMOVSD	%XMM6,(%R8,%RDX,8)

0x401b4a INC	%RDX

0x401b4d VMULSD	(%RSI,%RDX,8),%XMM0,%XMM7

0x401b52 VMOVSD	%XMM7,(%R8,%RDX,8)

0x401b58 INC	%RDX

0x401b5b CMP	%RDX,%RAX

0x401b5e JE	401bcf

(3) 0x401b60 VMULSD	(%RSI,%RDX,8),%XMM0,%XMM8

(3) 0x401b65 VMULSD	0x8(%RSI,%RDX,8),%XMM0,%XMM9

(3) 0x401b6b VMULSD	0x10(%RSI,%RDX,8),%XMM0,%XMM10

(3) 0x401b71 VMULSD	0x18(%RSI,%RDX,8),%XMM0,%XMM11

(3) 0x401b77 VMULSD	0x20(%RSI,%RDX,8),%XMM0,%XMM12

(3) 0x401b7d VMULSD	0x28(%RSI,%RDX,8),%XMM0,%XMM13

(3) 0x401b83 VMULSD	0x30(%RSI,%RDX,8),%XMM0,%XMM14

(3) 0x401b89 VMULSD	0x38(%RSI,%RDX,8),%XMM0,%XMM15

(3) 0x401b8f VMOVSD	%XMM8,(%R8,%RDX,8)

(3) 0x401b95 VMOVSD	%XMM9,0x8(%R8,%RDX,8)

(3) 0x401b9c VMOVSD	%XMM10,0x10(%R8,%RDX,8)

(3) 0x401ba3 VMOVSD	%XMM11,0x18(%R8,%RDX,8)

(3) 0x401baa VMOVSD	%XMM12,0x20(%R8,%RDX,8)

(3) 0x401bb1 VMOVSD	%XMM13,0x28(%R8,%RDX,8)

(3) 0x401bb8 VMOVSD	%XMM14,0x30(%R8,%RDX,8)

(3) 0x401bbf VMOVSD	%XMM15,0x38(%R8,%RDX,8)

(3) 0x401bc6 ADD	$0x8,%RDX

(3) 0x401bca CMP	%RDX,%RAX

(3) 0x401bcd JNE	401b60

0x401bcf POP	%RBX

0x401bd0 POP	%R12

0x401bd2 POP	%RBP

0x401bd3 RET

0x401bd4 NOPW	%CS:(%RAX,%RAX,1)

0x401bdf NOP

0x401be0 INC	%RAX

0x401be3 XOR	%EDX,%EDX

0x401be5 JMP	401a9b

0x401bea NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○98.95	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.05	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	stream.c:330-332
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330-332.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 5.17 cycles (2.32x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 3.00 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.25 cycles (1.30x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

7: multiply

The binary function is loading 64 bytes (8 double precision FP elements). The binary function is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	73
nb uops	72
loop length	289
used x86 registers	10
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.25	9.25	9.25	9.25	8.00	5.67	5.67	5.67	3.50	3.50	0.00	0.00	3.50	3.50
cycles	9.25	9.25	9.25	9.25	8.00	5.67	5.67	5.67	3.50	3.50	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	12.00
Dispatch	9.25
DIV/SQRT	7.00-12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

5% of peak load performance is reached (5.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.25 cycles (1.30x speedup).

ASM code

In the binary file, the address of the function is: 401a60

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %R12	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 401be0 <main._omp_fn.4+0x180>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 401bcf <main._omp_fn.4+0x16f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV $0x19a6860e0,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x4060e0,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND $0x7,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 401b60 <main._omp_fn.4+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b4d <main._omp_fn.4+0xed>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b3f <main._omp_fn.4+0xdf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b31 <main._omp_fn.4+0xd1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b23 <main._omp_fn.4+0xc3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b15 <main._omp_fn.4+0xb5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b07 <main._omp_fn.4+0xa7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM4,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM6,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401bcf <main._omp_fn.4+0x16f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 401a9b <main._omp_fn.4+0x3b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	stream.c:330-332
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 5.17 cycles (2.32x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

7: multiply

The binary function is loading 64 bytes (8 double precision FP elements). The binary function is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	73
nb uops	72
loop length	289
used x86 registers	10
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.25	9.25	9.25	9.25	8.00	5.67	5.67	5.67	3.50	3.50	0.00	0.00	3.50	3.50
cycles	9.25	9.25	9.25	9.25	8.00	5.67	5.67	5.67	3.50	3.50	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	12.00
Dispatch	9.25
DIV/SQRT	7.00-12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

5% of peak load performance is reached (5.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401a60

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %R12	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 401be0 <main._omp_fn.4+0x180>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 401bcf <main._omp_fn.4+0x16f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV $0x19a6860e0,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x4060e0,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND $0x7,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 401b60 <main._omp_fn.4+0x100>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b4d <main._omp_fn.4+0xed>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b3f <main._omp_fn.4+0xdf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b31 <main._omp_fn.4+0xd1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b23 <main._omp_fn.4+0xc3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b15 <main._omp_fn.4+0xb5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401b07 <main._omp_fn.4+0xa7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM4,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM6,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI,%RDX,8),%XMM0,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%R8,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401bcf <main._omp_fn.4+0x16f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 401a9b <main._omp_fn.4+0x3b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.4–	94.85	5.66
○Loop 3 - stream.c:332-332 - exec	94.85	5.57

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code