OV - exec - Loop 11

0x402ea0 LEA	-0x38(%R10,%RSI,1),%R11

0x402ea5 LEA	-0x38(%R10,%RDX,1),%R14

0x402eaa ADD	$0x40,%R10

0x402eae DEC	%R9

0x402eb1 VMULSD	(%R11),%XMM0,%XMM1    [1]

0x402eb6 VMULSD	0x8(%R11),%XMM0,%XMM2    [1]

0x402ebc VMULSD	0x10(%R11),%XMM0,%XMM3    [1]

0x402ec2 VMOVSD	%XMM1,(%R14)    [2]

0x402ec7 VMOVSD	%XMM2,0x8(%R14)    [2]

0x402ecd VMULSD	0x18(%R11),%XMM0,%XMM2    [1]

0x402ed3 VMOVSD	%XMM3,0x10(%R14)    [2]

0x402ed9 VMULSD	0x20(%R11),%XMM0,%XMM3    [1]

0x402edf VMOVSD	%XMM2,0x18(%R14)    [2]

0x402ee5 VMULSD	0x28(%R11),%XMM0,%XMM2    [1]

0x402eeb VMOVSD	%XMM3,0x20(%R14)    [2]

0x402ef1 VMULSD	0x30(%R11),%XMM0,%XMM3    [1]

0x402ef7 VMOVSD	%XMM2,0x28(%R14)    [2]

0x402efd VMULSD	0x38(%R11),%XMM0,%XMM2    [1]

0x402f03 VMOVSD	%XMM3,0x30(%R14)    [2]

0x402f09 VMOVSD	%XMM2,0x38(%R14)    [2]

0x402f0f JNE	402ea0

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c: 331 - 332

--------------------------------------------------------------------------------

331: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

332: 	    b[j] = scalar*c[j];

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.13
CQA speedup if FP arith vectorized	1.11
CQA speedup if fully vectorized	5.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P5, P6, P7,
Function	main.extracted.50
Source	stream.c:331-332
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.42
CQA cycles if fully vectorized	1.08
Front-end cycles	3.83
P0 cycles	1.25
P1 cycles	1.25
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	0.50
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.00
P13 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	23.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	1.33
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.13
CQA speedup if FP arith vectorized	1.11
CQA speedup if fully vectorized	5.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P5, P6, P7,
Function	main.extracted.50
Source	stream.c:331-332
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.42
CQA cycles if fully vectorized	1.08
Front-end cycles	3.83
P0 cycles	1.25
P1 cycles	1.25
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	0.50
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.00
P13 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	23.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	1.33
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main.extracted.50
Source file and lines	stream.c:331-332
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:331-332.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 5.33 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.08 cycles (5.54x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.00 cycles (1.50x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: multiply

The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	21
nb uops	23
loop length	113
used x86 registers	6
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.83 cycles
front end	3.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.25	1.25	1.00	1.00	0.50	6.00	6.00	6.00	4.00	4.00	0.00	0.00	4.00	4.00
cycles	1.25	1.25	1.00	1.00	0.50	6.00	6.00	6.00	4.00	4.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.83
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 402ea0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput	Vectorization
LEA -0x38(%R10,%RSI,1),%R11	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	2	0.50	N/A
LEA -0x38(%R10,%RDX,1),%R14	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	2	0.50	N/A
ADD $0x40,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
DEC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%R11),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMULSD 0x8(%R11),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMULSD 0x10(%R11),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM2,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMULSD 0x18(%R11),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,0x10(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMULSD 0x20(%R11),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,0x18(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMULSD 0x28(%R11),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,0x20(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMULSD 0x30(%R11),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,0x28(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMULSD 0x38(%R11),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,0x30(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM2,0x38(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
JNE 402ea0 <main.extracted.50+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	main.extracted.50
Source file and lines	stream.c:331-332
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:331-332.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 5.33 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.08 cycles (5.54x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.00 cycles (1.50x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: multiply

The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	21
nb uops	23
loop length	113
used x86 registers	6
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.83 cycles
front end	3.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.25	1.25	1.00	1.00	0.50	6.00	6.00	6.00	4.00	4.00	0.00	0.00	4.00	4.00
cycles	1.25	1.25	1.00	1.00	0.50	6.00	6.00	6.00	4.00	4.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.83
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 402ea0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput	Vectorization
LEA -0x38(%R10,%RSI,1),%R11	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	2	0.50	N/A
LEA -0x38(%R10,%RDX,1),%R14	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	2	0.50	N/A
ADD $0x40,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
DEC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%R11),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMULSD 0x8(%R11),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMULSD 0x10(%R11),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM2,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMULSD 0x18(%R11),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,0x10(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMULSD 0x20(%R11),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,0x18(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMULSD 0x28(%R11),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,0x20(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMULSD 0x30(%R11),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM2,0x28(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMULSD 0x38(%R11),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,0x30(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM2,0x38(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
JNE 402ea0 <main.extracted.50+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code