OV - exec - Function main.extracted.50

	Function: main.extracted.50	Module: exec	Source: stream.c:330-332	Coverage (incl. loops): 94.11% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c: 330 - 332

--------------------------------------------------------------------------------

330: #pragma omp parallel for

331: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

332: 	    b[j] = scalar*c[j];

0x402de0 PUSH	%RBP

0x402de1 MOV	%RSP,%RBP

0x402de4 PUSH	%R14

0x402de6 PUSH	%RBX

0x402de7 SUB	$0x20,%RSP

0x402deb MOVL	$0,-0x14(%RBP)

0x402df2 MOV	(%RDI),%EBX

0x402df4 MOVQ	$0,-0x28(%RBP)

0x402dfc MOVQ	$0x3344ffff,-0x20(%RBP)

0x402e04 MOVQ	$0x1,-0x30(%RBP)

0x402e0c SUB	$0x8,%RSP

0x402e10 LEA	-0x30(%RBP),%RAX

0x402e14 LEA	-0x28(%RBP),%R8

0x402e18 MOV	$0x4ceb88e20,%RDI

0x402e22 MOV	$0x401050,%R10

0x402e2c LEA	-0x14(%RBP),%RCX

0x402e30 LEA	-0x20(%RBP),%R9

0x402e34 MOV	%EBX,%ESI

0x402e36 MOV	$0x22,%EDX

0x402e3b PUSH	$0x1

0x402e3d PUSH	$0x1

0x402e3f PUSH	%RAX

0x402e40 CALL	%R10

0x402e43 ADD	$0x20,%RSP

0x402e47 MOV	-0x28(%RBP),%RAX

0x402e4b MOV	-0x20(%RBP),%R8

0x402e4f SUB	%RAX,%R8

0x402e52 JB	403037

0x402e58 LEA	0x1(%R8),%RDI

0x402e5c MOV	$0x4040d0,%RCX

0x402e66 MOV	$0x334906060,%RSI

0x402e70 MOV	$0x19a686060,%RDX

0x402e7a CMP	$0x7,%R8

0x402e7e JB	402f11

0x402e84 VMOVSD	(%RCX),%XMM0

0x402e88 LEA	0x38(,%RAX,8),%R10

0x402e90 MOV	%RDI,%R9

0x402e93 SHR	$0x3,%R9

0x402e97 NOPW	(%RAX,%RAX,1)

(11) 0x402ea0 LEA	-0x38(%R10,%RSI,1),%R11

(11) 0x402ea5 LEA	-0x38(%R10,%RDX,1),%R14

(11) 0x402eaa ADD	$0x40,%R10

(11) 0x402eae DEC	%R9

(11) 0x402eb1 VMULSD	(%R11),%XMM0,%XMM1

(11) 0x402eb6 VMULSD	0x8(%R11),%XMM0,%XMM2

(11) 0x402ebc VMULSD	0x10(%R11),%XMM0,%XMM3

(11) 0x402ec2 VMOVSD	%XMM1,(%R14)

(11) 0x402ec7 VMOVSD	%XMM2,0x8(%R14)

(11) 0x402ecd VMULSD	0x18(%R11),%XMM0,%XMM2

(11) 0x402ed3 VMOVSD	%XMM3,0x10(%R14)

(11) 0x402ed9 VMULSD	0x20(%R11),%XMM0,%XMM3

(11) 0x402edf VMOVSD	%XMM2,0x18(%R14)

(11) 0x402ee5 VMULSD	0x28(%R11),%XMM0,%XMM2

(11) 0x402eeb VMOVSD	%XMM3,0x20(%R14)

(11) 0x402ef1 VMULSD	0x30(%R11),%XMM0,%XMM3

(11) 0x402ef7 VMOVSD	%XMM2,0x28(%R14)

(11) 0x402efd VMULSD	0x38(%R11),%XMM0,%XMM2

(11) 0x402f03 VMOVSD	%XMM3,0x30(%R14)

(11) 0x402f09 VMOVSD	%XMM2,0x38(%R14)

(11) 0x402f0f JNE	402ea0

0x402f11 AND	$0x7ffffff8,%EDI

0x402f17 SUB	%RDI,%R8

0x402f1a CMP	$0x6,%R8

0x402f1e JA	403037

0x402f24 MOV	$0x404148,%R9

0x402f2e JMP	(%R9,%R8,8)

0x402f32 ADD	%RDI,%RAX

0x402f35 JMP	403029

0x402f3a ADD	%RDI,%RAX

0x402f3d JMP	402fa1

0x402f3f ADD	%RDI,%RAX

0x402f42 JMP	402fe5

0x402f47 ADD	%RDI,%RAX

0x402f4a JMP	402fc3

0x402f4c ADD	%RDI,%RAX

0x402f4f JMP	403007

0x402f54 ADD	%RDI,%RAX

0x402f57 JMP	402f7f

0x402f59 ADD	%RDI,%RAX

0x402f5c MOV	$0x334906090,%R8

0x402f66 MOV	$0x19a686090,%RDI

0x402f70 VMOVSD	(%R8,%RAX,8),%XMM0

0x402f76 VMULSD	(%RCX),%XMM0,%XMM0

0x402f7a VMOVSD	%XMM0,(%RDI,%RAX,8)

0x402f7f MOV	$0x334906088,%RDI

0x402f89 VMOVSD	(%RDI,%RAX,8),%XMM0

0x402f8e MOV	$0x19a686088,%RDI

0x402f98 VMULSD	(%RCX),%XMM0,%XMM0

0x402f9c VMOVSD	%XMM0,(%RDI,%RAX,8)

0x402fa1 MOV	$0x334906080,%RDI

0x402fab VMOVSD	(%RDI,%RAX,8),%XMM0

0x402fb0 MOV	$0x19a686080,%RDI

0x402fba VMULSD	(%RCX),%XMM0,%XMM0

0x402fbe VMOVSD	%XMM0,(%RDI,%RAX,8)

0x402fc3 MOV	$0x334906078,%RDI

0x402fcd VMOVSD	(%RDI,%RAX,8),%XMM0

0x402fd2 MOV	$0x19a686078,%RDI

0x402fdc VMULSD	(%RCX),%XMM0,%XMM0

0x402fe0 VMOVSD	%XMM0,(%RDI,%RAX,8)

0x402fe5 MOV	$0x334906070,%RDI

0x402fef VMOVSD	(%RDI,%RAX,8),%XMM0

0x402ff4 MOV	$0x19a686070,%RDI

0x402ffe VMULSD	(%RCX),%XMM0,%XMM0

0x403002 VMOVSD	%XMM0,(%RDI,%RAX,8)

0x403007 MOV	$0x334906068,%RDI

0x403011 VMOVSD	(%RDI,%RAX,8),%XMM0

0x403016 MOV	$0x19a686068,%RDI

0x403020 VMULSD	(%RCX),%XMM0,%XMM0

0x403024 VMOVSD	%XMM0,(%RDI,%RAX,8)

0x403029 VMOVSD	(%RSI,%RAX,8),%XMM0

0x40302e VMULSD	(%RCX),%XMM0,%XMM0

0x403032 VMOVSD	%XMM0,(%RDX,%RAX,8)

0x403037 MOV	$0x4ceb88e40,%RDI

0x403041 MOV	$0x401030,%RAX

0x40304b MOV	%EBX,%ESI

0x40304d ADD	$0x20,%RSP

0x403051 POP	%RBX

0x403052 POP	%R14

0x403054 POP	%RBP

0x403055 JMP	%RAX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_10

Source file and lines	stream.c:330-332
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330-332.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.67 to 7.33 cycles (2.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.67 to 1.87 cycles (8.89x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

7: multiply

The binary function is loading 148 bytes (18 double precision FP elements). The binary function is storing 84 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	100
loop length	518
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.67 cycles
front end	16.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.50	12.50	12.50	12.50	6.00	10.33	10.33	10.33	3.50	3.50	0.00	0.00	3.50	3.50
cycles	12.50	12.50	12.50	12.50	6.00	10.33	10.33	10.33	3.50	3.50	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.67
Dispatch	12.50
Overall L1	16.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	10%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.67 cycles. At this rate:

9% of peak load performance is reached (8.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (5.04 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.67 to 12.50 cycles (1.33x speedup).

ASM code

In the binary file, the address of the function is: 402de0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0x14(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88e20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x14(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x28(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
MOV -0x20(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
SUB %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JB 403037 <main.extracted.50+0x257>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%R8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4040d0,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334906060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x7,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 402f11 <main.extracted.50+0x131>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RCX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
LEA 0x38(,%RAX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $0x7ffffff8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x6,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 403037 <main.extracted.50+0x257>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x404148,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP (%R9,%R8,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 403029 <main.extracted.50+0x249>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 402fa1 <main.extracted.50+0x1c1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 402fe5 <main.extracted.50+0x205>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 402fc3 <main.extracted.50+0x1e3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 403007 <main.extracted.50+0x227>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 402f7f <main.extracted.50+0x19f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906090,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686090,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906088,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686088,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906080,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686080,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906078,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686078,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906070,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686070,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906068,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686068,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x4ceb88e40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_10

Source file and lines	stream.c:330-332
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.67 to 7.33 cycles (2.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

7: multiply

The binary function is loading 148 bytes (18 double precision FP elements). The binary function is storing 84 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	100
loop length	518
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.67 cycles
front end	16.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.50	12.50	12.50	12.50	6.00	10.33	10.33	10.33	3.50	3.50	0.00	0.00	3.50	3.50
cycles	12.50	12.50	12.50	12.50	6.00	10.33	10.33	10.33	3.50	3.50	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.67
Dispatch	12.50
Overall L1	16.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	10%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.67 cycles. At this rate:

9% of peak load performance is reached (8.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (5.04 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402de0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0x14(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88e20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x14(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x28(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
MOV -0x20(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
SUB %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JB 403037 <main.extracted.50+0x257>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%R8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4040d0,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334906060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x7,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 402f11 <main.extracted.50+0x131>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RCX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
LEA 0x38(,%RAX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $0x7ffffff8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x6,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 403037 <main.extracted.50+0x257>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x404148,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP (%R9,%R8,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 403029 <main.extracted.50+0x249>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 402fa1 <main.extracted.50+0x1c1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 402fe5 <main.extracted.50+0x205>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 402fc3 <main.extracted.50+0x1e3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 403007 <main.extracted.50+0x227>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JMP 402f7f <main.extracted.50+0x19f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906090,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686090,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906088,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686088,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906080,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686080,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906078,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686078,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906070,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686070,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906068,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686068,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x4ceb88e40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.50–	94.11	5.64
○Loop 11 - stream.c:331-332 - exec	94.11	5.56

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