OV - exec - Loop 3

	Loop Id: 3	Module: exec	Source: stream.c:292-292	Coverage: 0.67%

0x402526 VMOVUPD	(%R11),%ZMM14    [2]

0x40252c VMOVUPD	0x40(%R11),%ZMM0    [2]

0x402533 VMOVUPD	0x80(%R11),%ZMM2    [2]

0x40253a ADD	$0x200,%R11

0x402541 VMOVUPD	-0x140(%R11),%ZMM4    [1]

0x402548 VMOVUPD	-0x100(%R11),%ZMM6    [1]

0x40254f VMOVUPD	-0xc0(%R11),%ZMM8    [1]

0x402556 VMOVUPD	-0x80(%R11),%ZMM10    [1]

0x40255d VMOVUPD	-0x40(%R11),%ZMM12    [1]

0x402564 VADDPD	%ZMM14,%ZMM14,%ZMM15

0x40256a VADDPD	%ZMM0,%ZMM0,%ZMM1

0x402570 VADDPD	%ZMM2,%ZMM2,%ZMM3

0x402576 VADDPD	%ZMM4,%ZMM4,%ZMM5

0x40257c VMOVUPD	%ZMM15,-0x200(%R11)    [1]

0x402583 VADDPD	%ZMM6,%ZMM6,%ZMM7

0x402589 VADDPD	%ZMM8,%ZMM8,%ZMM9

0x40258f VMOVUPD	%ZMM1,-0x1c0(%R11)    [1]

0x402596 VMOVUPD	%ZMM3,-0x180(%R11)    [1]

0x40259d VADDPD	%ZMM10,%ZMM10,%ZMM11

0x4025a3 VADDPD	%ZMM12,%ZMM12,%ZMM13

0x4025a9 VMOVUPD	%ZMM5,-0x140(%R11)    [1]

0x4025b0 VMOVUPD	%ZMM7,-0x100(%R11)    [1]

0x4025b7 VMOVUPD	%ZMM9,-0xc0(%R11)    [1]

0x4025be VMOVUPD	%ZMM11,-0x80(%R11)    [1]

0x4025c5 VMOVUPD	%ZMM13,-0x40(%R11)    [1]

0x4025cc CMP	%RCX,%R11

0x4025cf JNE	402526

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c: 292 - 292

--------------------------------------------------------------------------------

292: 		a[j] = 2.0E0 * a[j];

Coverage (%)	Name	Source Location	Module
○98.94	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.06	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	P5, P6, P7, P10, P11, P12, P13,
Function	main._omp_fn.3
Source	stream.c:292-292
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	5.67
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	34.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	64.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	128.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	1.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	P5, P6, P7, P10, P11, P12, P13,
Function	main._omp_fn.3
Source	stream.c:292-292
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	5.67
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	34.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	64.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	128.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	1.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.3
Source file and lines	stream.c:292-292
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Reduce the number of FP add instructions
Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

64: addition or subtraction

The binary loop is loading 512 bytes (64 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	27
nb uops	34
loop length	175
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	5.33	5.33	5.33	0.00	0.00	4.00	4.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	0.00	0.00	8.00	8.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

66% of peak load performance is reached (64.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
100% of peak store performance is reached (64.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 402526

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD 0x40(%R11),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD 0x80(%R11),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
ADD $0x200,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD -0x140(%R11),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD -0x100(%R11),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD -0xc0(%R11),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD -0x80(%R11),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD -0x40(%R11),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD %ZMM14,%ZMM14,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VADDPD %ZMM0,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VADDPD %ZMM2,%ZMM2,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VADDPD %ZMM4,%ZMM4,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM15,-0x200(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VADDPD %ZMM6,%ZMM6,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VADDPD %ZMM8,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM1,-0x1c0(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD %ZMM3,-0x180(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VADDPD %ZMM10,%ZMM10,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VADDPD %ZMM12,%ZMM12,%ZMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM5,-0x140(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD %ZMM7,-0x100(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD %ZMM9,-0xc0(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD %ZMM11,-0x80(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD %ZMM13,-0x40(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
CMP %RCX,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 402526 <main._omp_fn.3+0x166>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	main._omp_fn.3
Source file and lines	stream.c:292-292
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Reduce the number of FP add instructions
Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:292

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

64: addition or subtraction

The binary loop is loading 512 bytes (64 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	27
nb uops	34
loop length	175
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	5.33	5.33	5.33	0.00	0.00	4.00	4.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	0.00	0.00	8.00	8.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

66% of peak load performance is reached (64.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
100% of peak store performance is reached (64.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 402526

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD 0x40(%R11),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD 0x80(%R11),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
ADD $0x200,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD -0x140(%R11),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD -0x100(%R11),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD -0xc0(%R11),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD -0x80(%R11),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VMOVUPD -0x40(%R11),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD %ZMM14,%ZMM14,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VADDPD %ZMM0,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VADDPD %ZMM2,%ZMM2,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VADDPD %ZMM4,%ZMM4,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM15,-0x200(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VADDPD %ZMM6,%ZMM6,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VADDPD %ZMM8,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM1,-0x1c0(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD %ZMM3,-0x180(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VADDPD %ZMM10,%ZMM10,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VADDPD %ZMM12,%ZMM12,%ZMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM5,-0x140(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD %ZMM7,-0x100(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD %ZMM9,-0xc0(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD %ZMM11,-0x80(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD %ZMM13,-0x40(%R11)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
CMP %RCX,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 402526 <main._omp_fn.3+0x166>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

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Front-end bottlenecks

ASM code

Vectorization

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Execution units bottlenecks

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Complex instructions

Details

Slow data structures access

Details

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code