OV - exec - Function main._omp

	Function: main._omp_fn.4	Module: exec	Source: stream.c:330-332	Coverage (incl. loops): 94.68% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c: 330 - 332

--------------------------------------------------------------------------------

330: #pragma omp parallel for

331: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

332: 	    b[j] = scalar*c[j];

0x402110 PUSH	%RBP

0x402111 MOV	$0x401060,%RAX

0x40211b MOV	%RSP,%RBP

0x40211e PUSH	%R12

0x402120 PUSH	%RBX

0x402121 MOV	%RDI,%RBX

0x402124 AND	$-0x40,%RSP

0x402128 CALL	%RAX

0x40212a MOVSXD	%EAX,%R12

0x40212d MOV	$0x401030,%RAX

0x402137 CALL	%RAX

0x402139 MOVSXD	%EAX,%RCX

0x40213c MOV	$0x33450000,%EAX

0x402141 CQTO

0x402143 IDIV	%R12

0x402146 CMP	%RDX,%RCX

0x402149 JL	402390

0x40214f IMUL	%RAX,%RCX

0x402153 ADD	%RCX,%RDX

0x402156 LEA	(%RAX,%RDX,1),%R10

0x40215a CMP	%R10,%RDX

0x40215d JGE	402372

0x402163 LEA	-0x1(%RAX),%RSI

0x402167 MOV	%RDX,%R11

0x40216a VMOVSD	(%RBX),%XMM1

0x40216e CMP	$0x6,%RSI

0x402172 JBE	4023a0

0x402178 MOV	%RAX,%R9

0x40217b LEA	(,%RDX,8),%RSI

0x402183 MOV	$0x406100,%R12

0x40218d MOV	$0x19a686100,%RBX

0x402197 SHR	$0x3,%R9

0x40219b VBROADCASTSD	%XMM1,%ZMM0

0x4021a1 SAL	$0x6,%R9

0x4021a5 LEA	-0x40(%R9),%R8

0x4021a9 LEA	(%R12,%RSI,1),%RDI

0x4021ad XOR	%ECX,%ECX

0x4021af ADD	%RBX,%RSI

0x4021b2 SHR	$0x6,%R8

0x4021b6 INC	%R8

0x4021b9 AND	$0x7,%R8D

0x4021bd JE	402271

0x4021c3 CMP	$0x1,%R8

0x4021c7 JE	402256

0x4021cd CMP	$0x2,%R8

0x4021d1 JE	402244

0x4021d3 CMP	$0x3,%R8

0x4021d7 JE	402232

0x4021d9 CMP	$0x4,%R8

0x4021dd JE	402220

0x4021df CMP	$0x5,%R8

0x4021e3 JE	40220e

0x4021e5 CMP	$0x6,%R8

0x4021e9 JE	4021fc

0x4021eb VMULPD	(%RDI),%ZMM0,%ZMM2

0x4021f1 MOV	$0x40,%ECX

0x4021f6 VMOVUPD	%ZMM2,(%RSI)

0x4021fc VMULPD	(%RDI,%RCX,1),%ZMM0,%ZMM3

0x402203 VMOVUPD	%ZMM3,(%RSI,%RCX,1)

0x40220a ADD	$0x40,%RCX

0x40220e VMULPD	(%RDI,%RCX,1),%ZMM0,%ZMM4

0x402215 VMOVUPD	%ZMM4,(%RSI,%RCX,1)

0x40221c ADD	$0x40,%RCX

0x402220 VMULPD	(%RDI,%RCX,1),%ZMM0,%ZMM5

0x402227 VMOVUPD	%ZMM5,(%RSI,%RCX,1)

0x40222e ADD	$0x40,%RCX

0x402232 VMULPD	(%RDI,%RCX,1),%ZMM0,%ZMM6

0x402239 VMOVUPD	%ZMM6,(%RSI,%RCX,1)

0x402240 ADD	$0x40,%RCX

0x402244 VMULPD	(%RDI,%RCX,1),%ZMM0,%ZMM7

0x40224b VMOVUPD	%ZMM7,(%RSI,%RCX,1)

0x402252 ADD	$0x40,%RCX

0x402256 VMULPD	(%RDI,%RCX,1),%ZMM0,%ZMM8

0x40225d VMOVUPD	%ZMM8,(%RSI,%RCX,1)

0x402264 ADD	$0x40,%RCX

0x402268 CMP	%R9,%RCX

0x40226b JE	4022ff

(2) 0x402271 VMULPD	(%RDI,%RCX,1),%ZMM0,%ZMM9

(2) 0x402278 VMOVUPD	%ZMM9,(%RSI,%RCX,1)

(2) 0x40227f VMULPD	0x40(%RDI,%RCX,1),%ZMM0,%ZMM10

(2) 0x402287 VMOVUPD	%ZMM10,0x40(%RSI,%RCX,1)

(2) 0x40228f VMULPD	0x80(%RDI,%RCX,1),%ZMM0,%ZMM11

(2) 0x402297 VMOVUPD	%ZMM11,0x80(%RSI,%RCX,1)

(2) 0x40229f VMULPD	0xc0(%RDI,%RCX,1),%ZMM0,%ZMM12

(2) 0x4022a7 VMOVUPD	%ZMM12,0xc0(%RSI,%RCX,1)

(2) 0x4022af VMULPD	0x100(%RDI,%RCX,1),%ZMM0,%ZMM13

(2) 0x4022b7 VMOVUPD	%ZMM13,0x100(%RSI,%RCX,1)

(2) 0x4022bf VMULPD	0x140(%RDI,%RCX,1),%ZMM0,%ZMM14

(2) 0x4022c7 VMOVUPD	%ZMM14,0x140(%RSI,%RCX,1)

(2) 0x4022cf VMULPD	0x180(%RDI,%RCX,1),%ZMM0,%ZMM15

(2) 0x4022d7 VMOVUPD	%ZMM15,0x180(%RSI,%RCX,1)

(2) 0x4022df VMULPD	0x1c0(%RDI,%RCX,1),%ZMM0,%ZMM2

(2) 0x4022e7 VMOVUPD	%ZMM2,0x1c0(%RSI,%RCX,1)

(2) 0x4022ef ADD	$0x200,%RCX

(2) 0x4022f6 CMP	%R9,%RCX

(2) 0x4022f9 JNE	402271

0x4022ff MOV	%RAX,%RDI

0x402302 AND	$-0x8,%RDI

0x402306 ADD	%RDI,%RDX

0x402309 CMP	%RDI,%RAX

0x40230c JE	402380

0x40230e SUB	%RDI,%RAX

0x402311 LEA	-0x1(%RAX),%RSI

0x402315 CMP	$0x2,%RSI

0x402319 JBE	40233c

0x40231b ADD	%R11,%RDI

0x40231e VBROADCASTSD	%XMM1,%YMM0

0x402323 MOV	%RAX,%R11

0x402326 VMULPD	(%R12,%RDI,8),%YMM0,%YMM3

0x40232c AND	$-0x4,%R11

0x402330 ADD	%R11,%RDX

0x402333 VMOVUPD	%YMM3,(%RBX,%RDI,8)

0x402338 TEST	$0x3,%AL

0x40233a JE	402380

0x40233c LEA	0x1(%RDX),%RAX

0x402340 VMULSD	(%R12,%RDX,8),%XMM1,%XMM4

0x402346 VMOVSD	%XMM4,(%RBX,%RDX,8)

0x40234b CMP	%RAX,%R10

0x40234e JLE	402380

0x402350 ADD	$0x2,%RDX

0x402354 VMULSD	(%R12,%RAX,8),%XMM1,%XMM5

0x40235a VMOVSD	%XMM5,(%RBX,%RAX,8)

0x40235f CMP	%RDX,%R10

0x402362 JLE	402380

0x402364 VMULSD	(%R12,%RDX,8),%XMM1,%XMM1

0x40236a VMOVSD	%XMM1,(%RBX,%RDX,8)

0x40236f VZEROUPPER

0x402372 LEA	-0x10(%RBP),%RSP

0x402376 POP	%RBX

0x402377 POP	%R12

0x402379 POP	%RBP

0x40237a RET

0x40237b NOPL	(%RAX,%RAX,1)

0x402380 VZEROUPPER

0x402383 LEA	-0x10(%RBP),%RSP

0x402387 POP	%RBX

0x402388 POP	%R12

0x40238a POP	%RBP

0x40238b RET

0x40238c NOPL	(%RAX)

0x402390 INC	%RAX

0x402393 XOR	%EDX,%EDX

0x402395 JMP	40214f

0x40239a NOPW	(%RAX,%RAX,1)

0x4023a0 XOR	%EDI,%EDI

0x4023a2 MOV	$0x406100,%R12

0x4023ac MOV	$0x19a686100,%RBX

0x4023b6 JMP	40230e

0x4023bb NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○98.95	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.05	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:330-332
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330-332.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.50 to 10.00 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 38% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 22.50 to 17.51 cycles (1.28x speedup).

Details

36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
72% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330
VMOVUPD: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time). 7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 63 FP arithmetical operations:

63: multiply

The binary function is loading 512 bytes (64 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	130
nb uops	135
loop length	546
used x86 registers	13
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	8
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.50 cycles
front end	22.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	17.25	17.25	17.25	17.25	12.00	8.33	8.33	8.33	6.00	5.50	1.50	0.00	9.00	9.00
cycles	17.25	17.25	17.25	17.25	12.00	10.67	10.67	10.67	10.00	8.50	1.50	0.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	22.50
Dispatch	17.25
DIV/SQRT	7.00-12.00
Overall L1	22.50

Vectorization ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	64%
load	66%
store	72%
mul	72%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	36%
load	66%
store	72%
mul	72%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	64%
load	66%
store	71%
mul	71%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	38%
load	66%
store	71%
mul	71%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.50 cycles. At this rate:

23% of peak load performance is reached (22.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (22.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.50 to 17.25 cycles (1.30x speedup).

ASM code

In the binary file, the address of the function is: 402110

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %R12	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 402390 <main._omp_fn.4+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 402372 <main._omp_fn.4+0x262>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVSD (%RBX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 4023a0 <main._omp_fn.4+0x290>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x406100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686100,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x3,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
SAL $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x40(%R9),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x6,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND $0x7,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 402271 <main._omp_fn.4+0x161>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402256 <main._omp_fn.4+0x146>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402244 <main._omp_fn.4+0x134>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402232 <main._omp_fn.4+0x122>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402220 <main._omp_fn.4+0x110>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40220e <main._omp_fn.4+0xfe>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4021fc <main._omp_fn.4+0xec>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULPD (%RDI),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
MOV $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %ZMM2,(%RSI)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM6,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM8,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022ff <main._omp_fn.4+0x1ef>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402380 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 40233c <main._omp_fn.4+0x22c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %R11,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMULPD (%R12,%RDI,8),%YMM0,%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
AND $-0x4,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %YMM3,(%RBX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (50.0%)
TEST $0x3,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402380 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%R12,%RDX,8),%XMM1,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM4,(%RBX,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402380 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%R12,%RAX,8),%XMM1,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402380 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD (%R12,%RDX,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%RBX,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40214f <main._omp_fn.4+0x3f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x406100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686100,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 40230e <main._omp_fn.4+0x1fe>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:330-332
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
72% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330
VMOVUPD: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:332

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:330

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 63 FP arithmetical operations:

63: multiply

The binary function is loading 512 bytes (64 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	130
nb uops	135
loop length	546
used x86 registers	13
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	8
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.50 cycles
front end	22.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	17.25	17.25	17.25	17.25	12.00	8.33	8.33	8.33	6.00	5.50	1.50	0.00	9.00	9.00
cycles	17.25	17.25	17.25	17.25	12.00	10.67	10.67	10.67	10.00	8.50	1.50	0.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	22.50
Dispatch	17.25
DIV/SQRT	7.00-12.00
Overall L1	22.50

Vectorization ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	64%
load	66%
store	72%
mul	72%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	36%
load	66%
store	72%
mul	72%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	64%
load	66%
store	71%
mul	71%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	38%
load	66%
store	71%
mul	71%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.50 cycles. At this rate:

23% of peak load performance is reached (22.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (22.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402110

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %R12	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 402390 <main._omp_fn.4+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 402372 <main._omp_fn.4+0x262>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVSD (%RBX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 4023a0 <main._omp_fn.4+0x290>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x406100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686100,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x3,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
SAL $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x40(%R9),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x6,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND $0x7,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 402271 <main._omp_fn.4+0x161>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402256 <main._omp_fn.4+0x146>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402244 <main._omp_fn.4+0x134>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402232 <main._omp_fn.4+0x122>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402220 <main._omp_fn.4+0x110>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40220e <main._omp_fn.4+0xfe>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4021fc <main._omp_fn.4+0xec>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULPD (%RDI),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
MOV $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %ZMM2,(%RSI)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM6,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULPD (%RDI,%RCX,1),%ZMM0,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM8,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022ff <main._omp_fn.4+0x1ef>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402380 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 40233c <main._omp_fn.4+0x22c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %R11,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMULPD (%R12,%RDI,8),%YMM0,%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
AND $-0x4,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %YMM3,(%RBX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (50.0%)
TEST $0x3,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402380 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%R12,%RDX,8),%XMM1,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM4,(%RBX,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402380 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%R12,%RAX,8),%XMM1,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402380 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD (%R12,%RDX,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%RBX,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40214f <main._omp_fn.4+0x3f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x406100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686100,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 40230e <main._omp_fn.4+0x1fe>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.4–	94.68	5.67
○Loop 2 - stream.c:332-332 - exec	94.68	5.59

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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