OV - exec - Function main.omp

	Function: main.omp_outlined.14	Module: exec	Source: stream.c:271-275	Coverage (incl. loops): 0.62% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c: 271 - 275

--------------------------------------------------------------------------------

271: #pragma omp parallel for

272:     for (j=0; j<STREAM_ARRAY_SIZE; j++) {

273: 	    a[j] = 1.0;

274: 	    b[j] = 2.0;

275: 	    c[j] = 0.0;

0x203210 PUSH	%RBP

0x203211 MOV	%RSP,%RBP

0x203214 PUSH	%R15

0x203216 PUSH	%R14

0x203218 PUSH	%R13

0x20321a PUSH	%R12

0x20321c PUSH	%RBX

0x20321d SUB	$0x28,%RSP

0x203221 MOV	(%RDI),%R14D

0x203224 LEA	0x333d(%RIP),%RBX

0x20322b MOVQ	$0,-0x40(%RBP)

0x203233 MOVQ	$0x3344ffff,-0x30(%RBP)

0x20323b MOVQ	$0x1,-0x48(%RBP)

0x203243 MOVL	$0,-0x34(%RBP)

0x20324a SUB	$0x8,%RSP

0x20324e MOV	$0x10b8,%RDI

0x203258 LEA	-0x48(%RBP),%RAX

0x20325c LEA	-0x34(%RBP),%RCX

0x203260 LEA	-0x40(%RBP),%R8

0x203264 LEA	-0x30(%RBP),%R9

0x203268 MOV	%R14D,%ESI

0x20326b MOV	$0x22,%EDX

0x203270 ADD	%RBX,%RDI

0x203273 PUSH	$0x1

0x203275 PUSH	$0x1

0x203277 PUSH	%RAX

0x203278 CALL	204370 <@plt_start@+0x80>

0x20327d ADD	$0x20,%RSP

0x203281 MOV	-0x30(%RBP),%RAX

0x203285 MOV	-0x40(%RBP),%R13

0x203289 MOV	$0x3344ffff,%R15D

0x20328f CMP	$0x3344ffff,%RAX

0x203295 CMOVL	%RAX,%R15

0x203299 MOV	%R15,-0x30(%RBP)

0x20329d CMP	%R15,%R13

0x2032a0 JG	203432

0x2032a6 MOV	$0x334501198,%RAX

0x2032b0 MOV	%R15,%R12

0x2032b3 SUB	%R13,%R12

0x2032b6 XOR	%ESI,%ESI

0x2032b8 ADD	%RBX,%RAX

0x2032bb LEA	0x8(,%R12,8),%RDX

0x2032c3 INC	%R12

0x2032c6 LEA	(%RAX,%R13,8),%RDI

0x2032ca CALL	204380 <@plt_start@+0x90>

0x2032cf MOV	$0x1198,%RAX

0x2032d9 MOV	$0x19a281198,%RCX

0x2032e3 CMP	$0x4,%R12

0x2032e7 JAE	2032f1

0x2032e9 MOV	%R13,%R8

0x2032ec JMP	2033fa

0x2032f1 MOV	$-0x5d70,%RSI

0x2032fb MOV	$-0x5d90,%RDI

0x203305 CMP	$0x20,%R12

0x203309 JAE	203312

0x20330b XOR	%EDX,%EDX

0x20330d JMP	2033aa

0x203312 VBROADCASTSD	(%RBX,%RSI,1),%ZMM0

0x203319 VBROADCASTSD	(%RBX,%RDI,1),%ZMM1

0x203320 LEA	(%RBX,%RAX,1),%R8

0x203324 LEA	(%RBX,%RCX,1),%R9

0x203328 MOV	%R12,%RDX

0x20332b AND	$-0x20,%RDX

0x20332f XOR	%R10D,%R10D

0x203332 LEA	0xc0(%R8,%R13,8),%R8

0x20333a LEA	0xc0(%R9,%R13,8),%R9

0x203342 NOPW	%CS:(%RAX,%RAX,1)

(4) 0x203350 VMOVUPS	%ZMM0,-0xc0(%R8,%R10,8)

(4) 0x203358 VMOVUPS	%ZMM0,-0x80(%R8,%R10,8)

(4) 0x203360 VMOVUPS	%ZMM0,-0x40(%R8,%R10,8)

(4) 0x203368 VMOVUPS	%ZMM1,-0xc0(%R9,%R10,8)

(4) 0x203370 VMOVUPS	%ZMM1,-0x80(%R9,%R10,8)

(4) 0x203378 VMOVUPS	%ZMM1,-0x40(%R9,%R10,8)

(4) 0x203380 VMOVUPS	%ZMM0,(%R8,%R10,8)

(4) 0x203387 VMOVUPS	%ZMM1,(%R9,%R10,8)

(4) 0x20338e ADD	$0x20,%R10

(4) 0x203392 CMP	%R10,%RDX

(4) 0x203395 JNE	203350

0x203397 CMP	%RDX,%R12

0x20339a JE	203432

0x2033a0 TEST	$0x1c,%R12B

0x2033a4 JE	20345c

0x2033aa VBROADCASTSD	(%RBX,%RSI,1),%YMM0

0x2033b0 VBROADCASTSD	(%RBX,%RDI,1),%YMM1

0x2033b6 LEA	(%RBX,%RAX,1),%R10

0x2033ba LEA	(%RBX,%RCX,1),%R11

0x2033be MOV	%R12,%R9

0x2033c1 AND	$-0x4,%R9

0x2033c5 LEA	(%R10,%R13,8),%R10

0x2033c9 LEA	(%R11,%R13,8),%R11

0x2033cd LEA	(%R13,%R9,1),%R8

0x2033d2 NOPW	%CS:(%RAX,%RAX,1)

(6) 0x2033e0 VMOVUPS	%YMM0,(%R10,%RDX,8)

(6) 0x2033e6 VMOVUPS	%YMM1,(%R11,%RDX,8)

(6) 0x2033ec ADD	$0x4,%RDX

(6) 0x2033f0 CMP	%RDX,%R9

(6) 0x2033f3 JNE	2033e0

0x2033f5 CMP	%R9,%R12

0x2033f8 JE	203432

0x2033fa DEC	%R8

0x2033fd ADD	%RBX,%RAX

0x203400 MOV	$0x3ff0000000000000,%RDX

0x20340a ADD	%RBX,%RCX

0x20340d MOV	$0x4000000000000000,%RSI

0x203417 NOPW	(%RAX,%RAX,1)

(5) 0x203420 MOV	%RDX,0x8(%RAX,%R8,8)

(5) 0x203425 MOV	%RSI,0x8(%RCX,%R8,8)

(5) 0x20342a INC	%R8

(5) 0x20342d CMP	%R15,%R8

(5) 0x203430 JL	203420

0x203432 MOV	$0x10d0,%RAX

0x20343c MOV	%R14D,%ESI

0x20343f ADD	%RAX,%RBX

0x203442 MOV	%RBX,%RDI

0x203445 VZEROUPPER

0x203448 CALL	204390 <@plt_start@+0xa0>

0x20344d ADD	$0x28,%RSP

0x203451 POP	%RBX

0x203452 POP	%R12

0x203454 POP	%R13

0x203456 POP	%R14

0x203458 POP	%R15

0x20345a POP	%RBP

0x20345b RET

0x20345c ADD	%RDX,%R13

0x20345f JMP	2032e9

0x203464 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:271-275
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:271-275.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.83 to 3.00 cycles (5.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 17.83 to 1.30 cycles (13.68x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:275
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:271

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	106
nb uops	107
loop length	498
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.83 cycles
front end	17.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	14.25	14.25	14.00	14.00	6.50	5.67	5.67	5.67	0.00	1.00	1.00	0.00	0.00	0.00
cycles	14.25	14.25	14.00	14.00	6.50	5.67	5.67	5.67	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.83
Dispatch	14.25
Overall L1	17.83

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	11%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.83 cycles. At this rate:

3% of peak load performance is reached (2.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.02 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.83 to 14.25 cycles (1.25x speedup).

ASM code

In the binary file, the address of the function is: 203210

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (6.3%)
LEA 0x333d(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x10b8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204370 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV -0x40(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV $0x3344ffff,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP $0x3344ffff,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RAX,%R15	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
CMP %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JG 203432 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV $0x334501198,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R13,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(,%R12,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R13,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CALL 204380 <@plt_start@+0x90>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
MOV $0x1198,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a281198,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
CMP $0x4,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 2032f1 <main.omp_outlined.14+0xe1>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV %R13,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 2033fa <main.omp_outlined.14+0x1ea>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
MOV $-0x5d70,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $-0x5d90,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
CMP $0x20,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 203312 <main.omp_outlined.14+0x102>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2033aa <main.omp_outlined.14+0x19a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
VBROADCASTSD (%RBX,%RSI,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1	scal (12.5%)
VBROADCASTSD (%RBX,%RDI,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1	scal (12.5%)
LEA (%RBX,%RAX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RCX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R8,%R13,8),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
LEA 0xc0(%R9,%R13,8),%R9	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203432 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%R12B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 20345c <main.omp_outlined.14+0x24c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD (%RBX,%RSI,1),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
VBROADCASTSD (%RBX,%RDI,1),%YMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
LEA (%RBX,%RAX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RCX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%R13,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%R13,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R13,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203432 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
DEC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x3ff0000000000000,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4000000000000000,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x10d0,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204390 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
ADD %RDX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JMP 2032e9 <main.omp_outlined.14+0xd9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:271-275
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.83 to 3.00 cycles (5.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:275
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0012/stream-scale/build/stream-scale/src/stream.c:271

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	106
nb uops	107
loop length	498
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.83 cycles
front end	17.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	14.25	14.25	14.00	14.00	6.50	5.67	5.67	5.67	0.00	1.00	1.00	0.00	0.00	0.00
cycles	14.25	14.25	14.00	14.00	6.50	5.67	5.67	5.67	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.83
Dispatch	14.25
Overall L1	17.83

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	11%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.83 cycles. At this rate:

3% of peak load performance is reached (2.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.02 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 203210

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (6.3%)
LEA 0x333d(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x10b8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204370 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV -0x40(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV $0x3344ffff,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP $0x3344ffff,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RAX,%R15	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
CMP %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JG 203432 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV $0x334501198,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R13,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(,%R12,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R13,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CALL 204380 <@plt_start@+0x90>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
MOV $0x1198,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a281198,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
CMP $0x4,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 2032f1 <main.omp_outlined.14+0xe1>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV %R13,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 2033fa <main.omp_outlined.14+0x1ea>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
MOV $-0x5d70,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $-0x5d90,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
CMP $0x20,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 203312 <main.omp_outlined.14+0x102>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2033aa <main.omp_outlined.14+0x19a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
VBROADCASTSD (%RBX,%RSI,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1	scal (12.5%)
VBROADCASTSD (%RBX,%RDI,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1	scal (12.5%)
LEA (%RBX,%RAX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RCX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R8,%R13,8),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
LEA 0xc0(%R9,%R13,8),%R9	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203432 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%R12B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 20345c <main.omp_outlined.14+0x24c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD (%RBX,%RSI,1),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
VBROADCASTSD (%RBX,%RDI,1),%YMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
LEA (%RBX,%RAX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RCX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%R13,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%R13,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R13,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203432 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
DEC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x3ff0000000000000,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4000000000000000,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x10d0,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204390 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
ADD %RDX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JMP 2032e9 <main.omp_outlined.14+0xd9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.14–	0.62	0.04
○Loop 4 - stream.c:273-274 - exec	0.62	0.04
○Loop 6 - stream.c:273-274 - exec	0.00	0.00
○Loop 5 - stream.c:272-274 - exec	0.00	0.00

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