OV - exec - Loop 3

	Loop Id: 3	Module: exec	Source: stream.c:320-320	Coverage: 94.81%

0x401a93 LEA	(,%RDX,8),%R10

0x401a9b LEA	0x8(,%RDX,8),%R11

0x401aa3 LEA	0x10(,%RDX,8),%RBX

0x401aab LEA	0x18(,%RDX,8),%RCX

0x401ab3 LEA	0x20(,%RDX,8),%RDI

0x401abb LEA	0x28(,%RDX,8),%R9

0x401ac3 VMOVSD	(%RSI,%R10,1),%XMM7    [2]

0x401ac9 VMOVSD	(%RSI,%R11,1),%XMM8    [2]

0x401acf VMOVSD	%XMM7,(%R8,%R10,1)    [1]

0x401ad5 VMOVSD	%XMM8,(%R8,%R11,1)    [1]

0x401adb LEA	0x30(,%RDX,8),%R10

0x401ae3 LEA	0x38(,%RDX,8),%R11

0x401aeb ADD	$0x8,%RDX

0x401aef VMOVSD	(%RSI,%RBX,1),%XMM9    [2]

0x401af4 VMOVSD	(%RSI,%RCX,1),%XMM10    [2]

0x401af9 VMOVSD	%XMM9,(%R8,%RBX,1)    [1]

0x401aff VMOVSD	(%RSI,%RDI,1),%XMM11    [2]

0x401b04 VMOVSD	%XMM10,(%R8,%RCX,1)    [1]

0x401b0a VMOVSD	(%RSI,%R9,1),%XMM12    [2]

0x401b10 VMOVSD	%XMM11,(%R8,%RDI,1)    [1]

0x401b16 VMOVSD	(%RSI,%R10,1),%XMM13    [2]

0x401b1c VMOVSD	%XMM12,(%R8,%R9,1)    [1]

0x401b22 VMOVSD	(%RSI,%R11,1),%XMM14    [2]

0x401b28 VMOVSD	%XMM13,(%R8,%R10,1)    [1]

0x401b2e VMOVSD	%XMM14,(%R8,%R11,1)    [1]

0x401b34 CMP	%RDX,%RAX

0x401b37 JNE	401a93

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c: 320 - 320

--------------------------------------------------------------------------------

320: 	    c[j] = a[j];

Coverage (%)	Name	Source Location	Module
○98.95	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.05	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P5, P6, P7,
Function	main._omp_fn.4
Source	stream.c:320-320
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.00
Front-end cycles	4.33
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	0.50
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	5.33
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.00
P13 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P5, P6, P7,
Function	main._omp_fn.4
Source	stream.c:320-320
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.00
Front-end cycles	4.33
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	0.50
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	5.33
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.00
P13 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.4
Source file and lines	stream.c:320-320
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.00 cycles (5.33x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.33 to 4.33 cycles (1.23x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	27
nb uops	26
loop length	170
used x86 registers	10
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.50	2.50	2.25	2.25	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	4.00	4.00
cycles	2.50	2.50	2.25	2.25	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.33
Dispatch	5.33
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (12.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401a93

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput	Vectorization
LEA (,%RDX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(,%RDX,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x10(,%RDX,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(,%RDX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x20(,%RDX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x28(,%RDX,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RSI,%R10,1),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD (%RSI,%R11,1),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,(%R8,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM8,(%R8,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
LEA 0x30(,%RDX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x38(,%RDX,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RSI,%RBX,1),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,1),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM9,(%R8,%RBX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RSI,%RDI,1),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM10,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RSI,%R9,1),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM11,(%R8,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RSI,%R10,1),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM12,(%R8,%R9,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RSI,%R11,1),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM13,(%R8,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM14,(%R8,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 401a93 <main._omp_fn.4+0x143>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A

Function	main._omp_fn.4
Source file and lines	stream.c:320-320
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.00 cycles (5.33x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.33 to 4.33 cycles (1.23x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	27
nb uops	26
loop length	170
used x86 registers	10
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.50	2.50	2.25	2.25	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	4.00	4.00
cycles	2.50	2.50	2.25	2.25	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.33
Dispatch	5.33
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (12.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401a93

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput	Vectorization
LEA (,%RDX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(,%RDX,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x10(,%RDX,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(,%RDX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x20(,%RDX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x28(,%RDX,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RSI,%R10,1),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD (%RSI,%R11,1),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,(%R8,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM8,(%R8,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
LEA 0x30(,%RDX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x38(,%RDX,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RSI,%RBX,1),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,1),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM9,(%R8,%RBX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RSI,%RDI,1),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM10,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RSI,%R9,1),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM11,(%R8,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RSI,%R10,1),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM12,(%R8,%R9,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RSI,%R11,1),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM13,(%R8,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM14,(%R8,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 401a93 <main._omp_fn.4+0x143>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code