OV - exec - Function main.extracted.50

	Function: main.extracted.50	Module: exec	Source: stream.c:318-320	Coverage (incl. loops): 94.10% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c: 318 - 320

--------------------------------------------------------------------------------

318: #pragma omp parallel for

319: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

320: 	    c[j] = a[j];

0x4030f0 PUSH	%RBP

0x4030f1 MOV	%RSP,%RBP

0x4030f4 PUSH	%RBX

0x4030f5 SUB	$0x28,%RSP

0x4030f9 MOVL	$0,-0xc(%RBP)

0x403100 MOV	(%RDI),%EBX

0x403102 MOVQ	$0,-0x20(%RBP)

0x40310a MOVQ	$0x3344ffff,-0x18(%RBP)

0x403112 MOVQ	$0x1,-0x28(%RBP)

0x40311a SUB	$0x8,%RSP

0x40311e LEA	-0x28(%RBP),%RAX

0x403122 MOV	%EBX,%ESI

0x403124 MOV	$0x4ceb88e20,%RDI

0x40312e MOV	$0x401050,%R10

0x403138 LEA	-0xc(%RBP),%RCX

0x40313c LEA	-0x20(%RBP),%R8

0x403140 LEA	-0x18(%RBP),%R9

0x403144 MOV	$0x22,%EDX

0x403149 PUSH	$0x1

0x40314b PUSH	$0x1

0x40314d PUSH	%RAX

0x40314e CALL	%R10

0x403151 ADD	$0x20,%RSP

0x403155 MOV	-0x20(%RBP),%RAX

0x403159 MOV	-0x18(%RBP),%RSI

0x40315d CMP	%RSI,%RAX

0x403160 JA	4032f2

0x403166 MOV	%RSI,%RDI

0x403169 SUB	%RAX,%RDI

0x40316c MOV	$0x334906060,%RCX

0x403176 MOV	$0x406060,%RDX

0x403180 INC	%RDI

0x403183 CMP	$0x8,%RDI

0x403187 JB	403211

0x40318d LEA	0x38(,%RAX,8),%R9

0x403195 MOV	%RDI,%R8

0x403198 SHR	$0x3,%R8

0x40319c NOPL	(%RAX)

(13) 0x4031a0 LEA	-0x38(%R9,%RDX,1),%R10

(13) 0x4031a5 LEA	-0x38(%R9,%RCX,1),%R11

(13) 0x4031aa ADD	$0x40,%R9

(13) 0x4031ae DEC	%R8

(13) 0x4031b1 VMOVSD	(%R10),%XMM0

(13) 0x4031b6 VMOVSD	0x8(%R10),%XMM1

(13) 0x4031bc VMOVSD	0x10(%R10),%XMM2

(13) 0x4031c2 VMOVSD	%XMM0,(%R11)

(13) 0x4031c7 VMOVSD	%XMM1,0x8(%R11)

(13) 0x4031cd VMOVSD	0x18(%R10),%XMM1

(13) 0x4031d3 VMOVSD	%XMM2,0x10(%R11)

(13) 0x4031d9 VMOVSD	0x20(%R10),%XMM2

(13) 0x4031df VMOVSD	%XMM1,0x18(%R11)

(13) 0x4031e5 VMOVSD	0x28(%R10),%XMM1

(13) 0x4031eb VMOVSD	%XMM2,0x20(%R11)

(13) 0x4031f1 VMOVSD	0x30(%R10),%XMM2

(13) 0x4031f7 VMOVSD	%XMM1,0x28(%R11)

(13) 0x4031fd VMOVSD	0x38(%R10),%XMM1

(13) 0x403203 VMOVSD	%XMM2,0x30(%R11)

(13) 0x403209 VMOVSD	%XMM1,0x38(%R11)

(13) 0x40320f JNE	4031a0

0x403211 AND	$0x7ffffff8,%EDI

0x403217 ADD	%RDI,%RAX

0x40321a SUB	%RAX,%RSI

0x40321d CMP	$0x6,%RSI

0x403221 JA	4032f2

0x403227 MOV	$0x404140,%RDI

0x403231 JMP	(%RDI,%RSI,8)

0x403234 MOV	$0x406090,%RSI

0x40323e VMOVSD	(%RSI,%RAX,8),%XMM0

0x403243 MOV	$0x334906090,%RSI

0x40324d VMOVSD	%XMM0,(%RSI,%RAX,8)

0x403252 MOV	$0x406088,%RSI

0x40325c VMOVSD	(%RSI,%RAX,8),%XMM0

0x403261 MOV	$0x334906088,%RSI

0x40326b VMOVSD	%XMM0,(%RSI,%RAX,8)

0x403270 MOV	$0x406080,%RSI

0x40327a VMOVSD	(%RSI,%RAX,8),%XMM0

0x40327f MOV	$0x334906080,%RSI

0x403289 VMOVSD	%XMM0,(%RSI,%RAX,8)

0x40328e MOV	$0x406078,%RSI

0x403298 VMOVSD	(%RSI,%RAX,8),%XMM0

0x40329d MOV	$0x334906078,%RSI

0x4032a7 VMOVSD	%XMM0,(%RSI,%RAX,8)

0x4032ac MOV	$0x406070,%RSI

0x4032b6 VMOVSD	(%RSI,%RAX,8),%XMM0

0x4032bb MOV	$0x334906070,%RSI

0x4032c5 VMOVSD	%XMM0,(%RSI,%RAX,8)

0x4032ca MOV	$0x406068,%RSI

0x4032d4 VMOVSD	(%RSI,%RAX,8),%XMM0

0x4032d9 MOV	$0x334906068,%RSI

0x4032e3 VMOVSD	%XMM0,(%RSI,%RAX,8)

0x4032e8 VMOVSD	(%RDX,%RAX,8),%XMM0

0x4032ed VMOVSD	%XMM0,(%RCX,%RAX,8)

0x4032f2 MOV	$0x4ceb88e40,%RDI

0x4032fc MOV	$0x401030,%RAX

0x403306 MOV	%EBX,%ESI

0x403308 ADD	$0x28,%RSP

0x40330c POP	%RBX

0x40330d POP	%RBP

0x40330e JMP	%RAX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	stream.c:318-320
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318-320.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.17 to 4.67 cycles (2.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.17 to 1.21 cycles (10.90x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 84 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	78
nb uops	79
loop length	431
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.17 cycles
front end	13.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.25	10.25	10.25	10.25	3.00	7.67	7.67	7.67	0.00	0.00	0.00	0.00	3.50	3.50
cycles	10.25	10.25	10.25	10.25	3.00	7.67	7.67	7.67	0.00	0.00	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.17
Dispatch	10.25
Overall L1	13.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.17 cycles. At this rate:

6% of peak load performance is reached (6.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (6.38 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.17 to 10.25 cycles (1.28x speedup).

ASM code

In the binary file, the address of the function is: 4030f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4ceb88e20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV -0x18(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4032f2 <main.extracted.50+0x202>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906060,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP $0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 403211 <main.extracted.50+0x121>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
LEA 0x38(,%RAX,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x3,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $0x7ffffff8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4032f2 <main.extracted.50+0x202>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV $0x404140,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
JMP (%RDI,%RSI,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	1	N/A
MOV $0x406090,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906090,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x406088,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906088,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x406080,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906080,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x406078,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906078,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x406070,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906070,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x406068,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906068,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RDX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x4ceb88e40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	stream.c:318-320
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.17 to 4.67 cycles (2.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 84 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	78
nb uops	79
loop length	431
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.17 cycles
front end	13.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.25	10.25	10.25	10.25	3.00	7.67	7.67	7.67	0.00	0.00	0.00	0.00	3.50	3.50
cycles	10.25	10.25	10.25	10.25	3.00	7.67	7.67	7.67	0.00	0.00	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.17
Dispatch	10.25
Overall L1	13.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.17 cycles. At this rate:

6% of peak load performance is reached (6.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (6.38 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4030f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4ceb88e20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV -0x18(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4032f2 <main.extracted.50+0x202>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906060,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP $0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 403211 <main.extracted.50+0x121>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
LEA 0x38(,%RAX,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x3,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $0x7ffffff8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4032f2 <main.extracted.50+0x202>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV $0x404140,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
JMP (%RDI,%RSI,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	1	N/A
MOV $0x406090,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906090,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x406088,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906088,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x406080,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906080,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x406078,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906078,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x406070,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906070,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x406068,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RSI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV $0x334906068,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RDX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1	scal (12.5%)
MOV $0x4ceb88e40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.50–	94.10	5.64
○Loop 13 - stream.c:319-320 - exec	94.10	5.56

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code