OV - exec - Function main._omp

	Function: main._omp_fn.4	Module: exec	Source: stream.c:318-320	Coverage (incl. loops): 94.63% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c: 318 - 320

--------------------------------------------------------------------------------

318: #pragma omp parallel for

319: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

320: 	    c[j] = a[j];

0x4020f0 PUSH	%RBP

0x4020f1 MOV	$0x401060,%RAX

0x4020fb MOV	%RSP,%RBP

0x4020fe PUSH	%R12

0x402100 PUSH	%RBX

0x402101 MOV	$0x401030,%R12

0x40210b AND	$-0x40,%RSP

0x40210f CALL	%RAX

0x402111 MOVSXD	%EAX,%RBX

0x402114 CALL	%R12

0x402117 MOVSXD	%EAX,%RCX

0x40211a MOV	$0x33450000,%EAX

0x40211f CQTO

0x402121 IDIV	%RBX

0x402124 CMP	%RDX,%RCX

0x402127 JL	402370

0x40212d IMUL	%RAX,%RCX

0x402131 ADD	%RCX,%RDX

0x402134 LEA	(%RAX,%RDX,1),%R10

0x402138 CMP	%R10,%RDX

0x40213b JGE	402349

0x402141 LEA	-0x1(%RAX),%RSI

0x402145 MOV	%RDX,%RBX

0x402148 CMP	$0x6,%RSI

0x40214c JBE	402380

0x402152 MOV	%RAX,%R9

0x402155 LEA	(,%RDX,8),%RSI

0x40215d MOV	$0x334906100,%R11

0x402167 MOV	$0x406100,%R12

0x402171 SHR	$0x3,%R9

0x402175 SAL	$0x6,%R9

0x402179 LEA	-0x40(%R9),%R8

0x40217d LEA	(%R11,%RSI,1),%RDI

0x402181 XOR	%ECX,%ECX

0x402183 ADD	%R12,%RSI

0x402186 SHR	$0x6,%R8

0x40218a INC	%R8

0x40218d AND	$0x7,%R8D

0x402191 JE	402245

0x402197 CMP	$0x1,%R8

0x40219b JE	40222a

0x4021a1 CMP	$0x2,%R8

0x4021a5 JE	402218

0x4021a7 CMP	$0x3,%R8

0x4021ab JE	402206

0x4021ad CMP	$0x4,%R8

0x4021b1 JE	4021f4

0x4021b3 CMP	$0x5,%R8

0x4021b7 JE	4021e2

0x4021b9 CMP	$0x6,%R8

0x4021bd JE	4021d0

0x4021bf VMOVUPD	(%RDI),%ZMM0

0x4021c5 MOV	$0x40,%ECX

0x4021ca VMOVUPD	%ZMM0,(%RSI)

0x4021d0 VMOVUPD	(%RDI,%RCX,1),%ZMM1

0x4021d7 VMOVUPD	%ZMM1,(%RSI,%RCX,1)

0x4021de ADD	$0x40,%RCX

0x4021e2 VMOVUPD	(%RDI,%RCX,1),%ZMM2

0x4021e9 VMOVUPD	%ZMM2,(%RSI,%RCX,1)

0x4021f0 ADD	$0x40,%RCX

0x4021f4 VMOVUPD	(%RDI,%RCX,1),%ZMM3

0x4021fb VMOVUPD	%ZMM3,(%RSI,%RCX,1)

0x402202 ADD	$0x40,%RCX

0x402206 VMOVUPD	(%RDI,%RCX,1),%ZMM4

0x40220d VMOVUPD	%ZMM4,(%RSI,%RCX,1)

0x402214 ADD	$0x40,%RCX

0x402218 VMOVUPD	(%RDI,%RCX,1),%ZMM5

0x40221f VMOVUPD	%ZMM5,(%RSI,%RCX,1)

0x402226 ADD	$0x40,%RCX

0x40222a VMOVUPD	(%RDI,%RCX,1),%ZMM6

0x402231 VMOVUPD	%ZMM6,(%RSI,%RCX,1)

0x402238 ADD	$0x40,%RCX

0x40223c CMP	%R9,%RCX

0x40223f JE	4022d3

(2) 0x402245 VMOVUPD	(%RDI,%RCX,1),%ZMM7

(2) 0x40224c VMOVUPD	%ZMM7,(%RSI,%RCX,1)

(2) 0x402253 VMOVUPD	0x40(%RDI,%RCX,1),%ZMM8

(2) 0x40225b VMOVUPD	%ZMM8,0x40(%RSI,%RCX,1)

(2) 0x402263 VMOVUPD	0x80(%RDI,%RCX,1),%ZMM9

(2) 0x40226b VMOVUPD	%ZMM9,0x80(%RSI,%RCX,1)

(2) 0x402273 VMOVUPD	0xc0(%RDI,%RCX,1),%ZMM10

(2) 0x40227b VMOVUPD	%ZMM10,0xc0(%RSI,%RCX,1)

(2) 0x402283 VMOVUPD	0x100(%RDI,%RCX,1),%ZMM11

(2) 0x40228b VMOVUPD	%ZMM11,0x100(%RSI,%RCX,1)

(2) 0x402293 VMOVUPD	0x140(%RDI,%RCX,1),%ZMM12

(2) 0x40229b VMOVUPD	%ZMM12,0x140(%RSI,%RCX,1)

(2) 0x4022a3 VMOVUPD	0x180(%RDI,%RCX,1),%ZMM13

(2) 0x4022ab VMOVUPD	%ZMM13,0x180(%RSI,%RCX,1)

(2) 0x4022b3 VMOVUPD	0x1c0(%RDI,%RCX,1),%ZMM14

(2) 0x4022bb VMOVUPD	%ZMM14,0x1c0(%RSI,%RCX,1)

(2) 0x4022c3 ADD	$0x200,%RCX

(2) 0x4022ca CMP	%R9,%RCX

(2) 0x4022cd JNE	402245

0x4022d3 MOV	%RAX,%RDI

0x4022d6 AND	$-0x8,%RDI

0x4022da ADD	%RDI,%RDX

0x4022dd CMP	%RDI,%RAX

0x4022e0 JE	402360

0x4022e2 SUB	%RDI,%RAX

0x4022e5 LEA	-0x1(%RAX),%RSI

0x4022e9 CMP	$0x2,%RSI

0x4022ed JBE	402310

0x4022ef ADD	%RBX,%RDI

0x4022f2 MOV	%RAX,%RBX

0x4022f5 SAL	$0x3,%RDI

0x4022f9 VMOVUPD	(%R11,%RDI,1),%YMM15

0x4022ff AND	$-0x4,%RBX

0x402303 ADD	%RBX,%RDX

0x402306 VMOVUPD	%YMM15,(%R12,%RDI,1)

0x40230c TEST	$0x3,%AL

0x40230e JE	402360

0x402310 LEA	0x1(%RDX),%RAX

0x402314 VMOVSD	(%R11,%RDX,8),%XMM0

0x40231a VMOVSD	%XMM0,(%R12,%RDX,8)

0x402320 CMP	%RAX,%R10

0x402323 JLE	402360

0x402325 ADD	$0x2,%RDX

0x402329 VMOVSD	(%R11,%RAX,8),%XMM1

0x40232f VMOVSD	%XMM1,(%R12,%RAX,8)

0x402335 CMP	%RDX,%R10

0x402338 JLE	402360

0x40233a VMOVSD	(%R11,%RDX,8),%XMM2

0x402340 VMOVSD	%XMM2,(%R12,%RDX,8)

0x402346 VZEROUPPER

0x402349 LEA	-0x10(%RBP),%RSP

0x40234d POP	%RBX

0x40234e POP	%R12

0x402350 POP	%RBP

0x402351 RET

0x402352 NOPW	%CS:(%RAX,%RAX,1)

0x40235d NOPL	(%RAX)

0x402360 VZEROUPPER

0x402363 LEA	-0x10(%RBP),%RSP

0x402367 POP	%RBX

0x402368 POP	%R12

0x40236a POP	%RBP

0x40236b RET

0x40236c NOPL	(%RAX)

0x402370 INC	%RAX

0x402373 XOR	%EDX,%EDX

0x402375 JMP	40212d

0x40237a NOPW	(%RAX,%RAX,1)

0x402380 XOR	%EDI,%EDI

0x402382 MOV	$0x334906100,%R11

0x40238c MOV	$0x406100,%R12

0x402396 JMP	4022e2

0x40239b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○98.95	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.05	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:318-320
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318-320.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.00 to 9.67 cycles (2.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 39% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 22.00 to 17.50 cycles (1.26x speedup).

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318
VMOVUPD: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 504 bytes. The binary function is storing 504 bytes.

General properties

nb instructions	128
nb uops	132
loop length	546
used x86 registers	13
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	7
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.00 cycles
front end	22.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	17.50	17.50	17.50	17.50	12.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	9.00	9.00
cycles	17.50	17.50	17.50	17.50	12.00	10.33	10.33	10.33	0.00	0.00	0.00	0.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	22.00
Dispatch	17.50
DIV/SQRT	7.00-12.00
Overall L1	22.00

Vectorization ratios

INT

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	72%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	37%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	71%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	39%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.00 cycles. At this rate:

23% of peak load performance is reached (22.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (22.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.00 to 17.50 cycles (1.26x speedup).

ASM code

In the binary file, the address of the function is: 4020f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401030,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL %R12	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 402370 <main._omp_fn.4+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 402349 <main._omp_fn.4+0x259>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 402380 <main._omp_fn.4+0x290>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906100,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x3,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SAL $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x40(%R9),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x6,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND $0x7,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 402245 <main._omp_fn.4+0x155>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40222a <main._omp_fn.4+0x13a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402218 <main._omp_fn.4+0x128>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402206 <main._omp_fn.4+0x116>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4021f4 <main._omp_fn.4+0x104>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4021e2 <main._omp_fn.4+0xf2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4021d0 <main._omp_fn.4+0xe0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%RDI),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
MOV $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %ZMM0,(%RSI)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
VMOVUPD (%RDI,%RCX,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM1,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM2,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM6,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022d3 <main._omp_fn.4+0x1e3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402360 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 402310 <main._omp_fn.4+0x220>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVUPD (%R11,%RDI,1),%YMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
AND $-0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %YMM15,(%R12,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (50.0%)
TEST $0x3,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402360 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R11,%RDX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402360 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R11,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,(%R12,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402360 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R11,%RDX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40212d <main._omp_fn.4+0x3d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x334906100,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 4022e2 <main._omp_fn.4+0x1f2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:318-320
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.00 to 9.67 cycles (2.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318
VMOVUPD: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:320

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0012/stream-copy/build/stream-copy/src/stream.c:318

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 504 bytes. The binary function is storing 504 bytes.

General properties

nb instructions	128
nb uops	132
loop length	546
used x86 registers	13
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	7
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.00 cycles
front end	22.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	17.50	17.50	17.50	17.50	12.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	9.00	9.00
cycles	17.50	17.50	17.50	17.50	12.00	10.33	10.33	10.33	0.00	0.00	0.00	0.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	22.00
Dispatch	17.50
DIV/SQRT	7.00-12.00
Overall L1	22.00

Vectorization ratios

INT

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	72%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	37%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	71%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	39%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.00 cycles. At this rate:

23% of peak load performance is reached (22.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (22.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4020f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401030,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL %R12	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 402370 <main._omp_fn.4+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 402349 <main._omp_fn.4+0x259>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 402380 <main._omp_fn.4+0x290>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906100,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x3,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SAL $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x40(%R9),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x6,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND $0x7,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 402245 <main._omp_fn.4+0x155>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40222a <main._omp_fn.4+0x13a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402218 <main._omp_fn.4+0x128>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402206 <main._omp_fn.4+0x116>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4021f4 <main._omp_fn.4+0x104>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4021e2 <main._omp_fn.4+0xf2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4021d0 <main._omp_fn.4+0xe0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%RDI),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
MOV $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %ZMM0,(%RSI)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
VMOVUPD (%RDI,%RCX,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM1,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM2,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%RDI,%RCX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM6,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022d3 <main._omp_fn.4+0x1e3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402360 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 402310 <main._omp_fn.4+0x220>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVUPD (%R11,%RDI,1),%YMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
AND $-0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %YMM15,(%R12,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (50.0%)
TEST $0x3,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402360 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R11,%RDX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402360 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R11,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,(%R12,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402360 <main._omp_fn.4+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R11,%RDX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40212d <main._omp_fn.4+0x3d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x334906100,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 4022e2 <main._omp_fn.4+0x1f2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.4–	94.63	5.49
○Loop 2 - stream.c:320-320 - exec	94.63	5.40

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Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code