OV - exec - Loop 21

	Loop Id: 21	Module: exec	Source: stream.c:476-479	Coverage: 0.34%

0x204580 VADDPD	-0x80(%R15,%RAX,8),%ZMM4,%ZMM16    [3]

0x204588 VADDPD	-0x40(%R15,%RAX,8),%ZMM4,%ZMM17    [3]

0x204590 VADDPD	(%R15,%RAX,8),%ZMM4,%ZMM18    [3]

0x204597 VADDPD	-0xc0(%R15,%RAX,8),%ZMM4,%ZMM15    [3]

0x20459f VADDPD	-0xc0(%R13,%RAX,8),%ZMM9,%ZMM25    [2]

0x2045a7 VADDPD	-0xc0(%R12,%RAX,8),%ZMM10,%ZMM24    [1]

0x2045af VXORPD	%ZMM23,%ZMM16,%ZMM20

0x2045b5 VXORPD	%ZMM23,%ZMM17,%ZMM21

0x2045bb VXORPD	%ZMM23,%ZMM18,%ZMM22

0x2045c1 VXORPD	%ZMM23,%ZMM15,%ZMM19

0x2045c7 VCMPPD	$0x6,%ZMM16,%ZMM20,%K2

0x2045ce VCMPPD	$0x6,%ZMM17,%ZMM21,%K3

0x2045d5 VCMPPD	$0x6,%ZMM18,%ZMM22,%K4

0x2045dc VCMPPD	$0x6,%ZMM15,%ZMM19,%K1

0x2045e3 VMOVAPD	%ZMM20,%ZMM16{%K2}

0x2045e9 VADDPD	%ZMM1,%ZMM16,%ZMM1

0x2045ef VMOVAPD	%ZMM21,%ZMM17{%K3}

0x2045f5 VADDPD	%ZMM2,%ZMM17,%ZMM2

0x2045fb VMOVAPD	%ZMM22,%ZMM18{%K4}

0x204601 VADDPD	%ZMM3,%ZMM18,%ZMM3

0x204607 VADDPD	-0x80(%R13,%RAX,8),%ZMM9,%ZMM16    [2]

0x20460f VADDPD	-0x40(%R13,%RAX,8),%ZMM9,%ZMM17    [2]

0x204617 VADDPD	(%R13,%RAX,8),%ZMM9,%ZMM18    [2]

0x20461f VMOVAPD	%ZMM19,%ZMM15{%K1}

0x204625 VXORPD	%ZMM23,%ZMM25,%ZMM19

0x20462b VADDPD	%ZMM0,%ZMM15,%ZMM0

0x204631 VCMPPD	$0x6,%ZMM25,%ZMM19,%K1

0x204638 VMOVAPD	%ZMM19,%ZMM25{%K1}

0x20463e VXORPD	%ZMM23,%ZMM24,%ZMM19

0x204644 VADDPD	%ZMM11,%ZMM25,%ZMM11

0x20464a VCMPPD	$0x6,%ZMM24,%ZMM19,%K1

0x204651 VMOVAPD	%ZMM19,%ZMM24{%K1}

0x204657 VADDPD	%ZMM5,%ZMM24,%ZMM5

0x20465d VXORPD	%ZMM23,%ZMM16,%ZMM20

0x204663 VXORPD	%ZMM23,%ZMM17,%ZMM21

0x204669 VXORPD	%ZMM23,%ZMM18,%ZMM22

0x20466f VCMPPD	$0x6,%ZMM16,%ZMM20,%K2

0x204676 VCMPPD	$0x6,%ZMM17,%ZMM21,%K3

0x20467d VCMPPD	$0x6,%ZMM18,%ZMM22,%K4

0x204684 VMOVAPD	%ZMM20,%ZMM16{%K2}

0x20468a VADDPD	%ZMM12,%ZMM16,%ZMM12

0x204690 VMOVAPD	%ZMM21,%ZMM17{%K3}

0x204696 VADDPD	%ZMM13,%ZMM17,%ZMM13

0x20469c VMOVAPD	%ZMM22,%ZMM18{%K4}

0x2046a2 VADDPD	%ZMM14,%ZMM18,%ZMM14

0x2046a8 VADDPD	-0x80(%R12,%RAX,8),%ZMM10,%ZMM16    [1]

0x2046b0 VADDPD	-0x40(%R12,%RAX,8),%ZMM10,%ZMM17    [1]

0x2046b8 VADDPD	(%R12,%RAX,8),%ZMM10,%ZMM18    [1]

0x2046bf ADD	$0x20,%RAX

0x2046c3 VXORPD	%ZMM23,%ZMM16,%ZMM20

0x2046c9 VXORPD	%ZMM23,%ZMM17,%ZMM21

0x2046cf VXORPD	%ZMM23,%ZMM18,%ZMM22

0x2046d5 VCMPPD	$0x6,%ZMM16,%ZMM20,%K2

0x2046dc VCMPPD	$0x6,%ZMM17,%ZMM21,%K3

0x2046e3 VCMPPD	$0x6,%ZMM18,%ZMM22,%K4

0x2046ea VMOVAPD	%ZMM20,%ZMM16{%K2}

0x2046f0 VMOVAPD	%ZMM21,%ZMM17{%K3}

0x2046f6 VMOVAPD	%ZMM22,%ZMM18{%K4}

0x2046fc VADDPD	%ZMM6,%ZMM16,%ZMM6

0x204702 VADDPD	%ZMM7,%ZMM17,%ZMM7

0x204708 VADDPD	%ZMM8,%ZMM18,%ZMM8

0x20470e CMP	$0x33450018,%RAX

0x204714 JNE	204580

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 476 - 479

--------------------------------------------------------------------------------

476: 	for (j=0; j<STREAM_ARRAY_SIZE; j++) {

477: 		aSumErr += abs(a[j] - aj);

478: 		bSumErr += abs(b[j] - bj);

479: 		cSumErr += abs(c[j] - cj);

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	checkSTREAMresults
Source	stream.c:476-479
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	10.33
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	24.00
P11 cycles	24.00
P12 cycles	0.00
P13 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	62.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	192.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	768.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	checkSTREAMresults
Source	stream.c:476-479
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	10.33
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	24.00
P11 cycles	24.00
P12 cycles	0.00
P13 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	62.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	192.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	768.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	checkSTREAMresults
Source file and lines	stream.c:476-479
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:476-479.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP add operations (the FP add unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 12.00 cycles (2.00x speedup).

Workaround

Reduce the number of FP add instructions

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

36 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

192: addition or subtraction

The binary loop is loading 768 bytes (96 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	62
loop length	410
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	26
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.33 cycles
front end	10.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	4.00	4.00	4.00	12.00	12.00	12.00	12.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	12.00	12.00	24.00	24.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	10.33
Dispatch	24.00
Data deps.	3.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 204580

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput	Vectorization
VADDPD -0x80(%R15,%RAX,8),%ZMM4,%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0x40(%R15,%RAX,8),%ZMM4,%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD (%R15,%RAX,8),%ZMM4,%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0xc0(%R15,%RAX,8),%ZMM4,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0xc0(%R13,%RAX,8),%ZMM9,%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0xc0(%R12,%RAX,8),%ZMM10,%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VXORPD %ZMM23,%ZMM16,%ZMM20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM17,%ZMM21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM15,%ZMM19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VCMPPD $0x6,%ZMM16,%ZMM20,%K2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM17,%ZMM21,%K3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM18,%ZMM22,%K4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM15,%ZMM19,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VMOVAPD %ZMM20,%ZMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM1,%ZMM16,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VMOVAPD %ZMM21,%ZMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM2,%ZMM17,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VMOVAPD %ZMM22,%ZMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM3,%ZMM18,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0x80(%R13,%RAX,8),%ZMM9,%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0x40(%R13,%RAX,8),%ZMM9,%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD (%R13,%RAX,8),%ZMM9,%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VMOVAPD %ZMM19,%ZMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VXORPD %ZMM23,%ZMM25,%ZMM19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM15,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VCMPPD $0x6,%ZMM25,%ZMM19,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VMOVAPD %ZMM19,%ZMM25{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VXORPD %ZMM23,%ZMM24,%ZMM19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM25,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VCMPPD $0x6,%ZMM24,%ZMM19,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VMOVAPD %ZMM19,%ZMM24{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM5,%ZMM24,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VXORPD %ZMM23,%ZMM16,%ZMM20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM17,%ZMM21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VCMPPD $0x6,%ZMM16,%ZMM20,%K2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM17,%ZMM21,%K3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM18,%ZMM22,%K4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VMOVAPD %ZMM20,%ZMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM12,%ZMM16,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VMOVAPD %ZMM21,%ZMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM13,%ZMM17,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VMOVAPD %ZMM22,%ZMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM14,%ZMM18,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0x80(%R12,%RAX,8),%ZMM10,%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0x40(%R12,%RAX,8),%ZMM10,%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD (%R12,%RAX,8),%ZMM10,%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
ADD $0x20,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPD %ZMM23,%ZMM16,%ZMM20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM17,%ZMM21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VCMPPD $0x6,%ZMM16,%ZMM20,%K2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM17,%ZMM21,%K3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM18,%ZMM22,%K4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VMOVAPD %ZMM20,%ZMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM21,%ZMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM22,%ZMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM6,%ZMM16,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD %ZMM7,%ZMM17,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD %ZMM8,%ZMM18,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
CMP $0x33450018,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 204580 <checkSTREAMresults+0xd0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	checkSTREAMresults
Source file and lines	stream.c:476-479
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP add instructions

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

36 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

192: addition or subtraction

The binary loop is loading 768 bytes (96 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	62
loop length	410
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	26
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.33 cycles
front end	10.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	4.00	4.00	4.00	12.00	12.00	12.00	12.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	12.00	12.00	24.00	24.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	10.33
Dispatch	24.00
Data deps.	3.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 204580

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput	Vectorization
VADDPD -0x80(%R15,%RAX,8),%ZMM4,%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0x40(%R15,%RAX,8),%ZMM4,%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD (%R15,%RAX,8),%ZMM4,%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0xc0(%R15,%RAX,8),%ZMM4,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0xc0(%R13,%RAX,8),%ZMM9,%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0xc0(%R12,%RAX,8),%ZMM10,%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VXORPD %ZMM23,%ZMM16,%ZMM20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM17,%ZMM21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM15,%ZMM19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VCMPPD $0x6,%ZMM16,%ZMM20,%K2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM17,%ZMM21,%K3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM18,%ZMM22,%K4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM15,%ZMM19,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VMOVAPD %ZMM20,%ZMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM1,%ZMM16,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VMOVAPD %ZMM21,%ZMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM2,%ZMM17,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VMOVAPD %ZMM22,%ZMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM3,%ZMM18,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0x80(%R13,%RAX,8),%ZMM9,%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0x40(%R13,%RAX,8),%ZMM9,%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD (%R13,%RAX,8),%ZMM9,%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VMOVAPD %ZMM19,%ZMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VXORPD %ZMM23,%ZMM25,%ZMM19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM15,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VCMPPD $0x6,%ZMM25,%ZMM19,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VMOVAPD %ZMM19,%ZMM25{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VXORPD %ZMM23,%ZMM24,%ZMM19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VADDPD %ZMM11,%ZMM25,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VCMPPD $0x6,%ZMM24,%ZMM19,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VMOVAPD %ZMM19,%ZMM24{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM5,%ZMM24,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VXORPD %ZMM23,%ZMM16,%ZMM20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM17,%ZMM21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VCMPPD $0x6,%ZMM16,%ZMM20,%K2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM17,%ZMM21,%K3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM18,%ZMM22,%K4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VMOVAPD %ZMM20,%ZMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM12,%ZMM16,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VMOVAPD %ZMM21,%ZMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM13,%ZMM17,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VMOVAPD %ZMM22,%ZMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM14,%ZMM18,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0x80(%R12,%RAX,8),%ZMM10,%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD -0x40(%R12,%RAX,8),%ZMM10,%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD (%R12,%RAX,8),%ZMM10,%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	3	1	vect (100.0%)
ADD $0x20,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPD %ZMM23,%ZMM16,%ZMM20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM17,%ZMM21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VXORPD %ZMM23,%ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	vect (100.0%)
VCMPPD $0x6,%ZMM16,%ZMM20,%K2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM17,%ZMM21,%K3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VCMPPD $0x6,%ZMM18,%ZMM22,%K4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	1	vect (100.0%)
VMOVAPD %ZMM20,%ZMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM21,%ZMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM22,%ZMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VADDPD %ZMM6,%ZMM16,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD %ZMM7,%ZMM17,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
VADDPD %ZMM8,%ZMM18,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	vect (100.0%)
CMP $0x33450018,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 204580 <checkSTREAMresults+0xd0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

▶Scalability Runs Description

Run 1x8	Number processes: 1Number nodes: NANumber processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threadsOMP_NUM_THREADS: 8
Run 1x64	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x128	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_NUM_THREADS: 128OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x160	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_NUM_THREADS: 160OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x192	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_NUM_THREADS: 192OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)	(1x128) Efficiency	(1x128) Potential Speed-Up (%)	(1x160) Efficiency	(1x160) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)
1	0	0.94	0	0.94	0	0.98	0	0.96	0	0.95	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x8	1	1	1	1	0.66000002622604	0.34364256262779
1x64	1	0.94	7.52	8	0.68500000238419	0.083152249455452
1x96	1	0.94	11.33	12	0.6800000667572	0.056553784757853
1x128	1	0.98	15.66	16	0.65499997138977	0.039190456271172
1x160	1	0.96	19.13	20	0.6700000166893	0.032304801046848
1x192	1	0.95	22.89	24	0.66999995708466	0.027687549591064

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency