OV - exec - Function main.omp

	Function: main.omp_outlined.14	Module: exec	Source: stream.c:271-275	Coverage (incl. loops): 0.08% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 271 - 275

--------------------------------------------------------------------------------

271: #pragma omp parallel for

272:     for (j=0; j<STREAM_ARRAY_SIZE; j++) {

273: 	    a[j] = 1.0;

274: 	    b[j] = 2.0;

275: 	    c[j] = 0.0;

0x2036e0 PUSH	%RBP

0x2036e1 MOV	%RSP,%RBP

0x2036e4 PUSH	%R15

0x2036e6 PUSH	%R14

0x2036e8 PUSH	%R13

0x2036ea PUSH	%R12

0x2036ec PUSH	%RBX

0x2036ed SUB	$0x28,%RSP

0x2036f1 MOV	(%RDI),%R14D

0x2036f4 LEA	0x2ad5(%RIP),%RBX

0x2036fb MOVQ	$0,-0x40(%RBP)

0x203703 MOVQ	$0x3344ffff,-0x30(%RBP)

0x20370b MOVQ	$0x1,-0x48(%RBP)

0x203713 MOVL	$0,-0x34(%RBP)

0x20371a SUB	$0x8,%RSP

0x20371e MOV	$0x10c0,%RDI

0x203728 LEA	-0x48(%RBP),%RAX

0x20372c LEA	-0x34(%RBP),%RCX

0x203730 LEA	-0x40(%RBP),%R8

0x203734 LEA	-0x30(%RBP),%R9

0x203738 MOV	%R14D,%ESI

0x20373b MOV	$0x22,%EDX

0x203740 ADD	%RBX,%RDI

0x203743 PUSH	$0x1

0x203745 PUSH	$0x1

0x203747 PUSH	%RAX

0x203748 CALL	204fc0 <@plt_start@+0x80>

0x20374d ADD	$0x20,%RSP

0x203751 MOV	-0x30(%RBP),%RAX

0x203755 MOV	-0x40(%RBP),%R13

0x203759 MOV	$0x3344ffff,%R15D

0x20375f CMP	$0x3344ffff,%RAX

0x203765 CMOVL	%RAX,%R15

0x203769 MOV	%R15,-0x30(%RBP)

0x20376d CMP	%R15,%R13

0x203770 JG	203902

0x203776 MOV	$0x334501270,%RAX

0x203780 MOV	%R15,%R12

0x203783 SUB	%R13,%R12

0x203786 XOR	%ESI,%ESI

0x203788 ADD	%RBX,%RAX

0x20378b LEA	0x8(,%R12,8),%RDX

0x203793 INC	%R12

0x203796 LEA	(%RAX,%R13,8),%RDI

0x20379a CALL	204fd0 <@plt_start@+0x90>

0x20379f MOV	$0x1270,%RAX

0x2037a9 MOV	$0x19a281270,%RCX

0x2037b3 CMP	$0x4,%R12

0x2037b7 JAE	2037c1

0x2037b9 MOV	%R13,%R8

0x2037bc JMP	2038ca

0x2037c1 MOV	$-0x5980,%RSI

0x2037cb MOV	$-0x59a0,%RDI

0x2037d5 CMP	$0x20,%R12

0x2037d9 JAE	2037e2

0x2037db XOR	%EDX,%EDX

0x2037dd JMP	20387a

0x2037e2 VBROADCASTSD	(%RBX,%RSI,1),%ZMM0

0x2037e9 VBROADCASTSD	(%RBX,%RDI,1),%ZMM1

0x2037f0 LEA	(%RBX,%RAX,1),%R8

0x2037f4 LEA	(%RBX,%RCX,1),%R9

0x2037f8 MOV	%R12,%RDX

0x2037fb AND	$-0x20,%RDX

0x2037ff XOR	%R10D,%R10D

0x203802 LEA	0xc0(%R8,%R13,8),%R8

0x20380a LEA	0xc0(%R9,%R13,8),%R9

0x203812 NOPW	%CS:(%RAX,%RAX,1)

(4) 0x203820 VMOVUPS	%ZMM0,-0xc0(%R8,%R10,8)

(4) 0x203828 VMOVUPS	%ZMM0,-0x80(%R8,%R10,8)

(4) 0x203830 VMOVUPS	%ZMM0,-0x40(%R8,%R10,8)

(4) 0x203838 VMOVUPS	%ZMM1,-0xc0(%R9,%R10,8)

(4) 0x203840 VMOVUPS	%ZMM1,-0x80(%R9,%R10,8)

(4) 0x203848 VMOVUPS	%ZMM1,-0x40(%R9,%R10,8)

(4) 0x203850 VMOVUPS	%ZMM0,(%R8,%R10,8)

(4) 0x203857 VMOVUPS	%ZMM1,(%R9,%R10,8)

(4) 0x20385e ADD	$0x20,%R10

(4) 0x203862 CMP	%R10,%RDX

(4) 0x203865 JNE	203820

0x203867 CMP	%RDX,%R12

0x20386a JE	203902

0x203870 TEST	$0x1c,%R12B

0x203874 JE	20392c

0x20387a VBROADCASTSD	(%RBX,%RSI,1),%YMM0

0x203880 VBROADCASTSD	(%RBX,%RDI,1),%YMM1

0x203886 LEA	(%RBX,%RAX,1),%R10

0x20388a LEA	(%RBX,%RCX,1),%R11

0x20388e MOV	%R12,%R9

0x203891 AND	$-0x4,%R9

0x203895 LEA	(%R10,%R13,8),%R10

0x203899 LEA	(%R11,%R13,8),%R11

0x20389d LEA	(%R13,%R9,1),%R8

0x2038a2 NOPW	%CS:(%RAX,%RAX,1)

(6) 0x2038b0 VMOVUPS	%YMM0,(%R10,%RDX,8)

(6) 0x2038b6 VMOVUPS	%YMM1,(%R11,%RDX,8)

(6) 0x2038bc ADD	$0x4,%RDX

(6) 0x2038c0 CMP	%RDX,%R9

(6) 0x2038c3 JNE	2038b0

0x2038c5 CMP	%R9,%R12

0x2038c8 JE	203902

0x2038ca DEC	%R8

0x2038cd ADD	%RBX,%RAX

0x2038d0 MOV	$0x3ff0000000000000,%RDX

0x2038da ADD	%RBX,%RCX

0x2038dd MOV	$0x4000000000000000,%RSI

0x2038e7 NOPW	(%RAX,%RAX,1)

(5) 0x2038f0 MOV	%RDX,0x8(%RAX,%R8,8)

(5) 0x2038f5 MOV	%RSI,0x8(%RCX,%R8,8)

(5) 0x2038fa INC	%R8

(5) 0x2038fd CMP	%R15,%R8

(5) 0x203900 JL	2038f0

0x203902 MOV	$0x10d8,%RAX

0x20390c MOV	%R14D,%ESI

0x20390f ADD	%RAX,%RBX

0x203912 MOV	%RBX,%RDI

0x203915 VZEROUPPER

0x203918 CALL	204fe0 <@plt_start@+0xa0>

0x20391d ADD	$0x28,%RSP

0x203921 POP	%RBX

0x203922 POP	%R12

0x203924 POP	%R13

0x203926 POP	%R14

0x203928 POP	%R15

0x20392a POP	%RBP

0x20392b RET

0x20392c ADD	%RDX,%R13

0x20392f JMP	2037b9

0x203934 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Coverage (%)	Name	Source Location	Module
►98.71+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
►1.29+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	unknown kernel region	unknown kernel region	kernel

Coverage (%)	Name	Source Location	Module
►99.26+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x8

Source file and lines	stream.c:271-275
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271-275.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.83 to 3.00 cycles (5.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 17.83 to 1.30 cycles (13.68x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:275
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	106
nb uops	107
loop length	498
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.83 cycles
front end	17.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	14.25	14.25	14.00	14.00	6.50	5.67	5.67	5.67	0.00	1.00	1.00	0.00	0.00	0.00
cycles	14.25	14.25	14.00	14.00	6.50	5.67	5.67	5.67	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.83
Dispatch	14.25
Overall L1	17.83

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	11%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.83 cycles. At this rate:

3% of peak load performance is reached (2.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.02 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.83 to 14.25 cycles (1.25x speedup).

ASM code

In the binary file, the address of the function is: 2036e0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (6.3%)
LEA 0x2ad5(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x10c0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204fc0 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV -0x40(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV $0x3344ffff,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP $0x3344ffff,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RAX,%R15	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
CMP %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JG 203902 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV $0x334501270,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R13,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(,%R12,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R13,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CALL 204fd0 <@plt_start@+0x90>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
MOV $0x1270,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a281270,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
CMP $0x4,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 2037c1 <main.omp_outlined.14+0xe1>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV %R13,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 2038ca <main.omp_outlined.14+0x1ea>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
MOV $-0x5980,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $-0x59a0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
CMP $0x20,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 2037e2 <main.omp_outlined.14+0x102>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 20387a <main.omp_outlined.14+0x19a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
VBROADCASTSD (%RBX,%RSI,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1	scal (12.5%)
VBROADCASTSD (%RBX,%RDI,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1	scal (12.5%)
LEA (%RBX,%RAX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RCX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R8,%R13,8),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
LEA 0xc0(%R9,%R13,8),%R9	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203902 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%R12B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 20392c <main.omp_outlined.14+0x24c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD (%RBX,%RSI,1),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
VBROADCASTSD (%RBX,%RDI,1),%YMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
LEA (%RBX,%RAX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RCX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%R13,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%R13,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R13,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203902 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
DEC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x3ff0000000000000,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4000000000000000,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x10d8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204fe0 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
ADD %RDX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JMP 2037b9 <main.omp_outlined.14+0xd9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x8

Source file and lines	stream.c:271-275
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.83 to 3.00 cycles (5.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:275
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	106
nb uops	107
loop length	498
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.83 cycles
front end	17.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	14.25	14.25	14.00	14.00	6.50	5.67	5.67	5.67	0.00	1.00	1.00	0.00	0.00	0.00
cycles	14.25	14.25	14.00	14.00	6.50	5.67	5.67	5.67	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.83
Dispatch	14.25
Overall L1	17.83

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	11%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.83 cycles. At this rate:

3% of peak load performance is reached (2.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.02 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 2036e0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (6.3%)
LEA 0x2ad5(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x10c0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204fc0 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV -0x40(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV $0x3344ffff,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
CMP $0x3344ffff,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RAX,%R15	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
CMP %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JG 203902 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV $0x334501270,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R13,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(,%R12,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R13,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CALL 204fd0 <@plt_start@+0x90>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
MOV $0x1270,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a281270,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
CMP $0x4,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 2037c1 <main.omp_outlined.14+0xe1>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV %R13,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 2038ca <main.omp_outlined.14+0x1ea>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
MOV $-0x5980,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $-0x59a0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
CMP $0x20,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 2037e2 <main.omp_outlined.14+0x102>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 20387a <main.omp_outlined.14+0x19a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
VBROADCASTSD (%RBX,%RSI,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1	scal (12.5%)
VBROADCASTSD (%RBX,%RDI,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	5	1	scal (12.5%)
LEA (%RBX,%RAX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RCX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R8,%R13,8),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
LEA 0xc0(%R9,%R13,8),%R9	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203902 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%R12B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 20392c <main.omp_outlined.14+0x24c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD (%RBX,%RSI,1),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
VBROADCASTSD (%RBX,%RDI,1),%YMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
LEA (%RBX,%RAX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RCX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%R13,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%R13,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R13,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203902 <main.omp_outlined.14+0x222>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
DEC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x3ff0000000000000,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4000000000000000,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x10d8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204fe0 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
ADD %RDX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JMP 2037b9 <main.omp_outlined.14+0xd9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

▶Scalability Runs Description

Run 1x8	Number processes: 1Number nodes: NANumber processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threadsOMP_NUM_THREADS: 8
Run 1x64	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x128	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_NUM_THREADS: 128OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x160	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_NUM_THREADS: 160OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x192	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/run/oneview_runs/multicore/aocc_2/oneview_run_1773744254OMP_NUM_THREADS: 192OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)	(1x128) Efficiency	(1x128) Potential Speed-Up (%)	(1x160) Efficiency	(1x160) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)
1	0	0.48	0.02	0.28	0.03	0.13	0.06	0.07	0.09	0.04	0.13

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x8	5	1	1	1	0.035000000149012	0.078100584447384
1x64	16	0.48	3.84	8	0.040000002831221	0.037023991346359
1x96	29	0.28	3.37	12	0.030000001192093	0.043247010558844
1x128	68	0.13	2	16	0.035000000149012	0.069705158472061
1x160	108	0.07	1.44	20	0.035000000149012	0.097878724336624
1x192	143	0.04	1.06	24	0.050000000745058	0.13533839583397

Name	Coverage (%)	Time (s)
▼main.omp_outlined.14–	0.08	0.02
○Loop 4 - stream.c:273-274 - exec	0.08	0.03
○Loop 6 - stream.c:273-274 - exec	0.00	0.00
○Loop 5 - stream.c:272-274 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency