OV - exec - Function main._omp

	Function: main._omp_fn.2	Module: exec	Source: stream.c:271-275	Coverage (incl. loops): 0.28% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 271 - 275

--------------------------------------------------------------------------------

271: #pragma omp parallel for

272:     for (j=0; j<STREAM_ARRAY_SIZE; j++) {

273: 	    a[j] = 1.0;

274: 	    b[j] = 2.0;

275: 	    c[j] = 0.0;

0x402460 PUSH	%RBP

0x402461 MOV	$0x401060,%RAX

0x40246b MOV	%RSP,%RBP

0x40246e PUSH	%RBX

0x40246f SUB	$0x8,%RSP

0x402473 CALL	%RAX

0x402475 MOVSXD	%EAX,%RBX

0x402478 MOV	$0x401030,%RAX

0x402482 CALL	%RAX

0x402484 MOVSXD	%EAX,%RCX

0x402487 MOV	$0x33450000,%EAX

0x40248c CQTO

0x40248e IDIV	%RBX

0x402491 CMP	%RDX,%RCX

0x402494 JL	4026f0

0x40249a IMUL	%RAX,%RCX

0x40249e ADD	%RCX,%RDX

0x4024a1 ADD	%RDX,%RAX

0x4024a4 CMP	%RAX,%RDX

0x4024a7 JGE	4026dc

0x4024ad MOV	%RAX,%RBX

0x4024b0 MOV	$0x404740,%R8

0x4024ba MOV	$0x404840,%R10

0x4024c4 MOV	$0x4048a8,%R11

0x4024ce SUB	%RDX,%RBX

0x4024d1 MOV	$0x334906180,%RDI

0x4024db MOV	$0x19a686180,%RSI

0x4024e5 MOV	$0x406180,%R9

0x4024ef AND	$0x7,%EBX

0x4024f2 VMOVSD	(%R8),%XMM2

0x4024f7 VMOVSD	(%R10),%XMM1

0x4024fc VMOVSD	(%R11),%XMM0

0x402501 JE	402605

0x402507 CMP	$0x1,%RBX

0x40250b JE	4025df

0x402511 CMP	$0x2,%RBX

0x402515 JE	4025c4

0x40251b CMP	$0x3,%RBX

0x40251f JE	4025a9

0x402525 CMP	$0x4,%RBX

0x402529 JE	40258c

0x40252b CMP	$0x5,%RBX

0x40252f JE	40256f

0x402531 CMP	$0x6,%RBX

0x402535 JE	402552

0x402537 LEA	(,%RDX,8),%RCX

0x40253f INC	%RDX

0x402542 VMOVSD	%XMM2,(%RDI,%RCX,1)

0x402547 VMOVSD	%XMM1,(%RSI,%RCX,1)

0x40254c VMOVSD	%XMM0,(%R9,%RCX,1)

0x402552 LEA	(,%RDX,8),%R8

0x40255a INC	%RDX

0x40255d VMOVSD	%XMM2,(%RDI,%R8,1)

0x402563 VMOVSD	%XMM1,(%RSI,%R8,1)

0x402569 VMOVSD	%XMM0,(%R9,%R8,1)

0x40256f LEA	(,%RDX,8),%R10

0x402577 INC	%RDX

0x40257a VMOVSD	%XMM2,(%RDI,%R10,1)

0x402580 VMOVSD	%XMM1,(%RSI,%R10,1)

0x402586 VMOVSD	%XMM0,(%R9,%R10,1)

0x40258c LEA	(,%RDX,8),%R11

0x402594 INC	%RDX

0x402597 VMOVSD	%XMM2,(%RDI,%R11,1)

0x40259d VMOVSD	%XMM1,(%RSI,%R11,1)

0x4025a3 VMOVSD	%XMM0,(%R9,%R11,1)

0x4025a9 LEA	(,%RDX,8),%RBX

0x4025b1 INC	%RDX

0x4025b4 VMOVSD	%XMM2,(%RDI,%RBX,1)

0x4025b9 VMOVSD	%XMM1,(%RSI,%RBX,1)

0x4025be VMOVSD	%XMM0,(%R9,%RBX,1)

0x4025c4 LEA	(,%RDX,8),%RCX

0x4025cc INC	%RDX

0x4025cf VMOVSD	%XMM2,(%RDI,%RCX,1)

0x4025d4 VMOVSD	%XMM1,(%RSI,%RCX,1)

0x4025d9 VMOVSD	%XMM0,(%R9,%RCX,1)

0x4025df LEA	(,%RDX,8),%R8

0x4025e7 INC	%RDX

0x4025ea VMOVSD	%XMM2,(%RDI,%R8,1)

0x4025f0 VMOVSD	%XMM1,(%RSI,%R8,1)

0x4025f6 VMOVSD	%XMM0,(%R9,%R8,1)

0x4025fc CMP	%RDX,%RAX

0x4025ff JE	4026dc

(8) 0x402605 LEA	(,%RDX,8),%R10

(8) 0x40260d LEA	0x8(,%RDX,8),%R11

(8) 0x402615 LEA	0x10(,%RDX,8),%RBX

(8) 0x40261d LEA	0x18(,%RDX,8),%RCX

(8) 0x402625 VMOVSD	%XMM2,(%RDI,%R10,1)

(8) 0x40262b VMOVSD	%XMM1,(%RSI,%R10,1)

(8) 0x402631 VMOVSD	%XMM0,(%R9,%R10,1)

(8) 0x402637 VMOVSD	%XMM2,(%RDI,%R11,1)

(8) 0x40263d VMOVSD	%XMM1,(%RSI,%R11,1)

(8) 0x402643 VMOVSD	%XMM0,(%R9,%R11,1)

(8) 0x402649 VMOVSD	%XMM2,(%RDI,%RBX,1)

(8) 0x40264e VMOVSD	%XMM1,(%RSI,%RBX,1)

(8) 0x402653 VMOVSD	%XMM0,(%R9,%RBX,1)

(8) 0x402659 LEA	0x20(,%RDX,8),%R8

(8) 0x402661 LEA	0x28(,%RDX,8),%R10

(8) 0x402669 LEA	0x30(,%RDX,8),%R11

(8) 0x402671 LEA	0x38(,%RDX,8),%RBX

(8) 0x402679 ADD	$0x8,%RDX

(8) 0x40267d VMOVSD	%XMM2,(%RDI,%RCX,1)

(8) 0x402682 VMOVSD	%XMM1,(%RSI,%RCX,1)

(8) 0x402687 VMOVSD	%XMM0,(%R9,%RCX,1)

(8) 0x40268d VMOVSD	%XMM2,(%RDI,%R8,1)

(8) 0x402693 VMOVSD	%XMM1,(%RSI,%R8,1)

(8) 0x402699 VMOVSD	%XMM0,(%R9,%R8,1)

(8) 0x40269f VMOVSD	%XMM2,(%RDI,%R10,1)

(8) 0x4026a5 VMOVSD	%XMM1,(%RSI,%R10,1)

(8) 0x4026ab VMOVSD	%XMM0,(%R9,%R10,1)

(8) 0x4026b1 VMOVSD	%XMM2,(%RDI,%R11,1)

(8) 0x4026b7 VMOVSD	%XMM1,(%RSI,%R11,1)

(8) 0x4026bd VMOVSD	%XMM0,(%R9,%R11,1)

(8) 0x4026c3 VMOVSD	%XMM2,(%RDI,%RBX,1)

(8) 0x4026c8 VMOVSD	%XMM1,(%RSI,%RBX,1)

(8) 0x4026cd VMOVSD	%XMM0,(%R9,%RBX,1)

(8) 0x4026d3 CMP	%RDX,%RAX

(8) 0x4026d6 JNE	402605

0x4026dc MOV	-0x8(%RBP),%RBX

0x4026e0 LEAVE

0x4026e1 RET

0x4026e2 NOPW	%CS:(%RAX,%RAX,1)

0x4026ed NOPL	(%RAX)

0x4026f0 INC	%RAX

0x4026f3 XOR	%EDX,%EDX

0x4026f5 JMP	40249a

0x4026fa NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○99.00	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.00	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_6

Source file and lines	stream.c:271-275
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271-275.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.17 to 10.50 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 15.17 to 3.00 cycles (5.06x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271
LEAVE: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	91
nb uops	91
loop length	457
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.17 cycles
front end	15.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.50	12.50	12.50	12.50	8.00	9.33	9.33	9.33	0.00	0.00	0.00	0.00	10.50	10.50
cycles	12.50	12.50	12.50	12.50	8.00	9.33	9.33	9.33	0.00	0.00	0.00	0.00	10.50	10.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	15.17
Dispatch	12.50
DIV/SQRT	7.00-12.00
Overall L1	15.17

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.17 cycles. At this rate:

2% of peak load performance is reached (2.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (11.08 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.17 to 12.50 cycles (1.21x speedup).

ASM code

In the binary file, the address of the function is: 402460

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 4026f0 <main._omp_fn.2+0x290>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 4026dc <main._omp_fn.2+0x27c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x404740,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x404840,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x4048a8,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RDX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906180,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686180,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406180,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $0x7,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
JE 402605 <main._omp_fn.2+0x1a5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4025df <main._omp_fn.2+0x17f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4025c4 <main._omp_fn.2+0x164>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4025a9 <main._omp_fn.2+0x149>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40258c <main._omp_fn.2+0x12c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40256f <main._omp_fn.2+0x10f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402552 <main._omp_fn.2+0xf2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RDX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%RBX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%RBX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%RBX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4026dc <main._omp_fn.2+0x27c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
LEAVE	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40249a <main._omp_fn.2+0x3a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_6

Source file and lines	stream.c:271-275
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271
LEAVE: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:271

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	91
nb uops	91
loop length	457
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.17 cycles
front end	15.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.50	12.50	12.50	12.50	8.00	9.33	9.33	9.33	0.00	0.00	0.00	0.00	10.50	10.50
cycles	12.50	12.50	12.50	12.50	8.00	9.33	9.33	9.33	0.00	0.00	0.00	0.00	10.50	10.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	15.17
Dispatch	12.50
DIV/SQRT	7.00-12.00
Overall L1	15.17

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.17 cycles. At this rate:

2% of peak load performance is reached (2.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (11.08 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402460

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 4026f0 <main._omp_fn.2+0x290>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 4026dc <main._omp_fn.2+0x27c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x404740,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x404840,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x4048a8,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RDX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906180,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686180,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406180,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $0x7,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
JE 402605 <main._omp_fn.2+0x1a5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4025df <main._omp_fn.2+0x17f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4025c4 <main._omp_fn.2+0x164>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4025a9 <main._omp_fn.2+0x149>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40258c <main._omp_fn.2+0x12c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40256f <main._omp_fn.2+0x10f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402552 <main._omp_fn.2+0xf2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RDX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%RBX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%RBX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%RBX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
LEA (,%RDX,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM2,(%RDI,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM1,(%RSI,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM0,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4026dc <main._omp_fn.2+0x27c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
LEAVE	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40249a <main._omp_fn.2+0x3a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.2–	0.28	0.07
○Loop 8 - stream.c:273-275 - exec	0.28	0.07

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