OV - exec - Function main.extracted.60

	Function: main.extracted.60	Module: exec	Source: stream.c:342-344	Coverage (incl. loops): 27.37% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 342 - 344

--------------------------------------------------------------------------------

342: #pragma omp parallel for

343: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

344: 	    c[j] = a[j]+b[j];

0x403180 PUSH	%RBP

0x403181 MOV	%RSP,%RBP

0x403184 PUSH	%R14

0x403186 PUSH	%RBX

0x403187 SUB	$0x20,%RSP

0x40318b MOVL	$0,-0x14(%RBP)

0x403192 MOV	(%RDI),%EBX

0x403194 MOVQ	$0,-0x28(%RBP)

0x40319c MOVQ	$0x3344ffff,-0x20(%RBP)

0x4031a4 MOVQ	$0x1,-0x30(%RBP)

0x4031ac SUB	$0x8,%RSP

0x4031b0 LEA	-0x30(%RBP),%RAX

0x4031b4 LEA	-0x28(%RBP),%R8

0x4031b8 LEA	-0x20(%RBP),%R9

0x4031bc MOV	$0x4ceb891e0,%RDI

0x4031c6 MOV	$0x401050,%R10

0x4031d0 LEA	-0x14(%RBP),%RCX

0x4031d4 MOV	%EBX,%ESI

0x4031d6 MOV	$0x22,%EDX

0x4031db PUSH	$0x1

0x4031dd PUSH	$0x1

0x4031df PUSH	%RAX

0x4031e0 CALL	%R10

0x4031e3 ADD	$0x20,%RSP

0x4031e7 MOV	-0x20(%RBP),%RAX

0x4031eb MOV	-0x28(%RBP),%R8

0x4031ef MOV	%RAX,%R9

0x4031f2 SUB	%R8,%R9

0x4031f5 JB	40329e

0x4031fb INC	%R9

0x4031fe MOV	$0x19a686060,%RDX

0x403208 MOV	$0x406060,%RSI

0x403212 MOV	$0x334906060,%RDI

0x40321c MOV	%R9,%RCX

0x40321f AND	$0x7ffffffc,%RCX

0x403226 JE	403266

0x403228 LEA	(,%R8,8),%R10

0x403230 XOR	%R11D,%R11D

0x403233 NOPW	%CS:(%RAX,%RAX,1)

(18) 0x403240 LEA	(%R10,%R11,8),%R14

(18) 0x403244 ADD	$0x4,%R11

(18) 0x403248 VMOVUPD	(%RDX,%R14,1),%YMM0

(18) 0x40324e VADDPD	(%RSI,%R14,1),%YMM0,%YMM0

(18) 0x403254 VMOVUPD	%YMM0,(%RDI,%R14,1)

(18) 0x40325a CMP	%RCX,%R11

(18) 0x40325d JB	403240

0x40325f CMP	%RCX,%R9

0x403262 JNE	403268

0x403264 JMP	40329e

0x403266 XOR	%ECX,%ECX

0x403268 SUB	%RCX,%RAX

0x40326b ADD	%R8,%RCX

0x40326e SUB	%R8,%RAX

0x403271 SAL	$0x3,%RCX

0x403275 XOR	%R8D,%R8D

0x403278 INC	%RAX

0x40327b NOPL	(%RAX,%RAX,1)

(17) 0x403280 LEA	(%RCX,%R8,8),%R9

(17) 0x403284 INC	%R8

(17) 0x403287 VMOVSD	(%RDX,%R9,1),%XMM0

(17) 0x40328d VADDSD	(%RSI,%R9,1),%XMM0,%XMM0

(17) 0x403293 VMOVSD	%XMM0,(%RDI,%R9,1)

(17) 0x403299 CMP	%R8,%RAX

(17) 0x40329c JNE	403280

0x40329e MOV	$0x4ceb89200,%RDI

0x4032a8 MOV	$0x401030,%RAX

0x4032b2 MOV	%EBX,%ESI

0x4032b4 ADD	$0x20,%RSP

0x4032b8 POP	%RBX

0x4032b9 POP	%R14

0x4032bb POP	%RBP

0x4032bc VZEROUPPER

0x4032bf JMP	%RAX

0x4032c1 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_9

Source file and lines	stream.c:342-344
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342-344.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.67 to 0.69 cycles (13.91x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	60
nb uops	58
loop length	275
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.25	7.25	7.25	7.25	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.25	7.25	7.25	7.25	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.67
Dispatch	7.25
Overall L1	9.67

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.67 cycles. At this rate:

2% of peak load performance is reached (2.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.90 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.67 to 7.25 cycles (1.33x speedup).

ASM code

In the binary file, the address of the function is: 403180

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0x14(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4ceb891e0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x14(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x28(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 40329e <main.extracted.60+0x11e>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x19a686060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x406060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x334906060,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffffc,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 403266 <main.extracted.60+0xe6>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA (,%R8,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 403268 <main.extracted.60+0xe8>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 40329e <main.extracted.60+0x11e>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SUB %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SUB %R8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x4ceb89200,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_9

Source file and lines	stream.c:342-344
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	60
nb uops	58
loop length	275
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.25	7.25	7.25	7.25	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.25	7.25	7.25	7.25	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.67
Dispatch	7.25
Overall L1	9.67

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.67 cycles. At this rate:

2% of peak load performance is reached (2.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.90 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 403180

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0x14(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4ceb891e0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x14(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x28(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 40329e <main.extracted.60+0x11e>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x19a686060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x406060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x334906060,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffffc,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 403266 <main.extracted.60+0xe6>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA (,%R8,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 403268 <main.extracted.60+0xe8>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 40329e <main.extracted.60+0x11e>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SUB %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SUB %R8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x4ceb89200,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.60–	27.37	7.41
○Loop 18 - stream.c:343-344 - exec	27.37	7.28
○Loop 17 - stream.c:343-344 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code