OV - exec - Function main.extracted.55

	Function: main.extracted.55	Module: exec	Source: stream.c:330-332	Coverage (incl. loops): 21.02% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 330 - 332

--------------------------------------------------------------------------------

330: #pragma omp parallel for

331: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

332: 	    b[j] = scalar*c[j];

0x403040 PUSH	%RBP

0x403041 MOV	%RSP,%RBP

0x403044 PUSH	%R14

0x403046 PUSH	%RBX

0x403047 SUB	$0x20,%RSP

0x40304b MOVL	$0,-0x14(%RBP)

0x403052 MOV	(%RDI),%EBX

0x403054 MOVQ	$0,-0x28(%RBP)

0x40305c MOVQ	$0x3344ffff,-0x20(%RBP)

0x403064 MOVQ	$0x1,-0x30(%RBP)

0x40306c SUB	$0x8,%RSP

0x403070 LEA	-0x30(%RBP),%RAX

0x403074 MOV	$0x4ceb89180,%RDI

0x40307e LEA	-0x20(%RBP),%R9

0x403082 MOV	$0x401050,%R10

0x40308c LEA	-0x14(%RBP),%RCX

0x403090 LEA	-0x28(%RBP),%R8

0x403094 MOV	%EBX,%ESI

0x403096 MOV	$0x22,%EDX

0x40309b PUSH	$0x1

0x40309d PUSH	$0x1

0x40309f PUSH	%RAX

0x4030a0 CALL	%R10

0x4030a3 ADD	$0x20,%RSP

0x4030a7 MOV	-0x20(%RBP),%RAX

0x4030ab MOV	-0x28(%RBP),%RDI

0x4030af MOV	%RAX,%R9

0x4030b2 SUB	%RDI,%R9

0x4030b5 JB	403158

0x4030bb INC	%R9

0x4030be MOV	$0x334906060,%RDX

0x4030c8 MOV	$0x4040d0,%R8

0x4030d2 MOV	$0x19a686060,%RSI

0x4030dc MOV	%R9,%RCX

0x4030df AND	$0x7ffffffc,%RCX

0x4030e6 JE	403120

0x4030e8 VBROADCASTSD	(%R8),%YMM0

0x4030ed LEA	(,%RDI,8),%R10

0x4030f5 XOR	%R11D,%R11D

0x4030f8 NOPL	(%RAX,%RAX,1)

(16) 0x403100 LEA	(%R10,%R11,8),%R14

(16) 0x403104 ADD	$0x4,%R11

(16) 0x403108 VMULPD	(%RDX,%R14,1),%YMM0,%YMM1

(16) 0x40310e VMOVUPD	%YMM1,(%RSI,%R14,1)

(16) 0x403114 CMP	%RCX,%R11

(16) 0x403117 JB	403100

0x403119 CMP	%RCX,%R9

0x40311c JNE	403122

0x40311e JMP	403158

0x403120 XOR	%ECX,%ECX

0x403122 VMOVSD	(%R8),%XMM0

0x403127 SUB	%RCX,%RAX

0x40312a ADD	%RDI,%RCX

0x40312d SUB	%RDI,%RAX

0x403130 SAL	$0x3,%RCX

0x403134 XOR	%EDI,%EDI

0x403136 INC	%RAX

0x403139 NOPL	(%RAX)

(15) 0x403140 LEA	(%RCX,%RDI,8),%R8

(15) 0x403144 INC	%RDI

(15) 0x403147 VMULSD	(%RDX,%R8,1),%XMM0,%XMM1

(15) 0x40314d VMOVSD	%XMM1,(%RSI,%R8,1)

(15) 0x403153 CMP	%RDI,%RAX

(15) 0x403156 JNE	403140

0x403158 MOV	$0x4ceb891a0,%RDI

0x403162 MOV	$0x401030,%RAX

0x40316c MOV	%EBX,%ESI

0x40316e ADD	$0x20,%RSP

0x403172 POP	%RBX

0x403173 POP	%R14

0x403175 POP	%RBP

0x403176 VZEROUPPER

0x403179 JMP	%RAX

0x40317b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_9

Source file and lines	stream.c:330-332
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:330-332.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 1.67 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:330

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	62
nb uops	60
loop length	271
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.00 cycles
front end	10.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.25	7.25	7.25	7.25	3.00	3.33	3.33	3.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.25	7.25	7.25	7.25	3.00	3.33	3.33	3.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.00
Dispatch	7.25
Overall L1	10.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

INT

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.00 cycles. At this rate:

3% of peak load performance is reached (3.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.00 to 7.25 cycles (1.38x speedup).

ASM code

In the binary file, the address of the function is: 403040

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0x14(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4ceb89180,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x20(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x14(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x28(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 403158 <main.extracted.55+0x118>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x334906060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x4040d0,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffffc,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 403120 <main.extracted.55+0xe0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
VBROADCASTSD (%R8),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
LEA (,%RDI,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 403122 <main.extracted.55+0xe2>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 403158 <main.extracted.55+0x118>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVSD (%R8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x4ceb891a0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_9

Source file and lines	stream.c:330-332
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 1.67 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:330

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	62
nb uops	60
loop length	271
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.00 cycles
front end	10.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.25	7.25	7.25	7.25	3.00	3.33	3.33	3.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.25	7.25	7.25	7.25	3.00	3.33	3.33	3.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.00
Dispatch	7.25
Overall L1	10.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

INT

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.00 cycles. At this rate:

3% of peak load performance is reached (3.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 403040

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0x14(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4ceb89180,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x20(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x14(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x28(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 403158 <main.extracted.55+0x118>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x334906060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x4040d0,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffffc,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 403120 <main.extracted.55+0xe0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
VBROADCASTSD (%R8),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
LEA (,%RDI,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 403122 <main.extracted.55+0xe2>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 403158 <main.extracted.55+0x118>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVSD (%R8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x4ceb891a0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.55–	21.02	5.69
○Loop 16 - stream.c:331-332 - exec	21.02	5.59
○Loop 15 - stream.c:331-332 - exec	0.00	0.00

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Execution units bottlenecks

512-bits vectorization

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code