OV - exec - Function main.extracted.50

	Function: main.extracted.50	Module: exec	Source: stream.c:318-320	Coverage (incl. loops): 20.93% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 318 - 320

--------------------------------------------------------------------------------

318: #pragma omp parallel for

319: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

320: 	    c[j] = a[j];

0x402f10 PUSH	%RBP

0x402f11 MOV	%RSP,%RBP

0x402f14 PUSH	%RBX

0x402f15 SUB	$0x28,%RSP

0x402f19 MOVL	$0,-0xc(%RBP)

0x402f20 MOV	(%RDI),%EBX

0x402f22 MOVQ	$0,-0x20(%RBP)

0x402f2a MOVQ	$0x3344ffff,-0x18(%RBP)

0x402f32 MOVQ	$0x1,-0x28(%RBP)

0x402f3a SUB	$0x8,%RSP

0x402f3e LEA	-0x28(%RBP),%RAX

0x402f42 MOV	$0x4ceb89120,%RDI

0x402f4c LEA	-0x20(%RBP),%R8

0x402f50 MOV	$0x401050,%R10

0x402f5a LEA	-0xc(%RBP),%RCX

0x402f5e LEA	-0x18(%RBP),%R9

0x402f62 MOV	%EBX,%ESI

0x402f64 MOV	$0x22,%EDX

0x402f69 PUSH	$0x1

0x402f6b PUSH	$0x1

0x402f6d PUSH	%RAX

0x402f6e CALL	%R10

0x402f71 ADD	$0x20,%RSP

0x402f75 MOV	-0x18(%RBP),%RAX

0x402f79 MOV	-0x20(%RBP),%RDI

0x402f7d MOV	%RAX,%R8

0x402f80 SUB	%RDI,%R8

0x402f83 JB	403018

0x402f89 INC	%R8

0x402f8c MOV	$0x406060,%RDX

0x402f96 MOV	$0x334906060,%RSI

0x402fa0 MOV	%R8,%RCX

0x402fa3 AND	$0x7ffffffc,%RCX

0x402faa JE	402fe0

0x402fac LEA	(,%RDI,8),%R9

0x402fb4 XOR	%R10D,%R10D

0x402fb7 NOPW	(%RAX,%RAX,1)

(14) 0x402fc0 LEA	(%R9,%R10,8),%R11

(14) 0x402fc4 ADD	$0x4,%R10

(14) 0x402fc8 VMOVUPS	(%RDX,%R11,1),%YMM0

(14) 0x402fce VMOVUPS	%YMM0,(%RSI,%R11,1)

(14) 0x402fd4 CMP	%RCX,%R10

(14) 0x402fd7 JB	402fc0

0x402fd9 CMP	%RCX,%R8

0x402fdc JNE	402fe2

0x402fde JMP	403018

0x402fe0 XOR	%ECX,%ECX

0x402fe2 SUB	%RCX,%RAX

0x402fe5 ADD	%RDI,%RCX

0x402fe8 SUB	%RDI,%RAX

0x402feb SAL	$0x3,%RCX

0x402fef XOR	%EDI,%EDI

0x402ff1 INC	%RAX

0x402ff4 NOPW	%CS:(%RAX,%RAX,1)

(13) 0x403000 LEA	(%RCX,%RDI,8),%R8

(13) 0x403004 INC	%RDI

(13) 0x403007 VMOVSD	(%RDX,%R8,1),%XMM0

(13) 0x40300d VMOVSD	%XMM0,(%RSI,%R8,1)

(13) 0x403013 CMP	%RDI,%RAX

(13) 0x403016 JNE	403000

0x403018 MOV	$0x4ceb89140,%RDI

0x403022 MOV	$0x401030,%RAX

0x40302c MOV	%EBX,%ESI

0x40302e ADD	$0x28,%RSP

0x403032 POP	%RBX

0x403033 POP	%RBP

0x403034 VZEROUPPER

0x403037 JMP	%RAX

0x403039 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_9

Source file and lines	stream.c:318-320
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:318-320.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.17 to 0.66 cycles (13.82x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:318

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	57
nb uops	55
loop length	255
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.00	7.00	7.00	7.00	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.00	7.00	7.00	7.00	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.17
Dispatch	7.00
Overall L1	9.17

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.17 cycles. At this rate:

2% of peak load performance is reached (2.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (3.05 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.17 to 7.00 cycles (1.31x speedup).

ASM code

In the binary file, the address of the function is: 402f10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4ceb89120,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x18(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x20(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 403018 <main.extracted.50+0x108>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x406060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x334906060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffffc,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 402fe0 <main.extracted.50+0xd0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA (,%RDI,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RCX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 402fe2 <main.extracted.50+0xd2>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 403018 <main.extracted.50+0x108>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SUB %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x4ceb89140,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_9

Source file and lines	stream.c:318-320
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:318

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	57
nb uops	55
loop length	255
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.00	7.00	7.00	7.00	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	7.00	7.00	7.00	7.00	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.17
Dispatch	7.00
Overall L1	9.17

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.17 cycles. At this rate:

2% of peak load performance is reached (2.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (3.05 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402f10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4ceb89120,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x18(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x20(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 403018 <main.extracted.50+0x108>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x406060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x334906060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffffc,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 402fe0 <main.extracted.50+0xd0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA (,%RDI,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RCX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 402fe2 <main.extracted.50+0xd2>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 403018 <main.extracted.50+0x108>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SUB %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x4ceb89140,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.50–	20.93	5.67
○Loop 14 - stream.c:319-320 - exec	20.93	5.57
○Loop 13 - stream.c:319-320 - exec	0.00	0.00

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