OV - exec - Function main.extracted.45

	Function: main.extracted.45	Module: exec	Source: stream.c:290-292	Coverage (incl. loops): 0.15% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 290 - 292

--------------------------------------------------------------------------------

290: #pragma omp parallel for

291:     for (j = 0; j < STREAM_ARRAY_SIZE; j++)

292: 		a[j] = 2.0E0 * a[j];

0x402df0 PUSH	%RBP

0x402df1 MOV	%RSP,%RBP

0x402df4 PUSH	%RBX

0x402df5 SUB	$0x28,%RSP

0x402df9 MOVL	$0,-0xc(%RBP)

0x402e00 MOV	(%RDI),%EBX

0x402e02 MOVQ	$0,-0x20(%RBP)

0x402e0a MOVQ	$0x3344ffff,-0x18(%RBP)

0x402e12 MOVQ	$0x1,-0x28(%RBP)

0x402e1a SUB	$0x8,%RSP

0x402e1e LEA	-0x28(%RBP),%RAX

0x402e22 MOV	$0x4ceb890c0,%RDI

0x402e2c MOV	%EBX,%ESI

0x402e2e MOV	$0x401050,%R10

0x402e38 LEA	-0xc(%RBP),%RCX

0x402e3c LEA	-0x20(%RBP),%R8

0x402e40 LEA	-0x18(%RBP),%R9

0x402e44 MOV	$0x22,%EDX

0x402e49 PUSH	$0x1

0x402e4b PUSH	$0x1

0x402e4d PUSH	%RAX

0x402e4e CALL	%R10

0x402e51 ADD	$0x20,%RSP

0x402e55 MOV	-0x18(%RBP),%RAX

0x402e59 MOV	-0x20(%RBP),%RSI

0x402e5d MOV	%RAX,%RDI

0x402e60 SUB	%RSI,%RDI

0x402e63 JB	402eea

0x402e69 INC	%RDI

0x402e6c MOV	$0x406060,%RDX

0x402e76 MOV	%RDI,%RCX

0x402e79 AND	$0x7ffffffc,%RCX

0x402e80 JE	402eb4

0x402e82 LEA	(,%RSI,8),%R8

0x402e8a XOR	%R9D,%R9D

0x402e8d NOPL	(%RAX)

(12) 0x402e90 LEA	(%R8,%R9,8),%R10

(12) 0x402e94 ADD	$0x4,%R9

(12) 0x402e98 VMOVUPD	(%RDX,%R10,1),%YMM0

(12) 0x402e9e VADDPD	%YMM0,%YMM0,%YMM0

(12) 0x402ea2 VMOVUPD	%YMM0,(%RDX,%R10,1)

(12) 0x402ea8 CMP	%RCX,%R9

(12) 0x402eab JB	402e90

0x402ead CMP	%RCX,%RDI

0x402eb0 JNE	402eb6

0x402eb2 JMP	402eea

0x402eb4 XOR	%ECX,%ECX

0x402eb6 SUB	%RCX,%RAX

0x402eb9 ADD	%RSI,%RCX

0x402ebc SUB	%RSI,%RAX

0x402ebf SAL	$0x3,%RCX

0x402ec3 XOR	%ESI,%ESI

0x402ec5 INC	%RAX

0x402ec8 NOPL	(%RAX,%RAX,1)

(11) 0x402ed0 LEA	(%RCX,%RSI,8),%RDI

(11) 0x402ed4 INC	%RSI

(11) 0x402ed7 VMOVSD	(%RDX,%RDI,1),%XMM0

(11) 0x402edc VADDSD	%XMM0,%XMM0,%XMM0

(11) 0x402ee0 VMOVSD	%XMM0,(%RDX,%RDI,1)

(11) 0x402ee5 CMP	%RSI,%RAX

(11) 0x402ee8 JNE	402ed0

0x402eea MOV	$0x4ceb890e0,%RDI

0x402ef4 MOV	$0x401030,%RAX

0x402efe MOV	%EBX,%ESI

0x402f00 ADD	$0x28,%RSP

0x402f04 POP	%RBX

0x402f05 POP	%RBP

0x402f06 VZEROUPPER

0x402f09 JMP	%RAX

0x402f0b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_9

Source file and lines	stream.c:290-292
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:290-292.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.00 to 0.63 cycles (14.22x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:290

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	56
nb uops	54
loop length	233
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.75	6.75	6.75	6.75	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.75	6.75	6.75	6.75	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.00
Dispatch	6.75
Overall L1	9.00

Vectorization ratios

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

2% of peak load performance is reached (2.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (3.11 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.00 to 6.75 cycles (1.33x speedup).

ASM code

In the binary file, the address of the function is: 402df0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4ceb890c0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x18(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x20(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JB 402eea <main.extracted.45+0xfa>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x406060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffffc,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 402eb4 <main.extracted.45+0xc4>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA (,%RSI,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RCX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 402eb6 <main.extracted.45+0xc6>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 402eea <main.extracted.45+0xfa>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SUB %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SUB %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x4ceb890e0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_9

Source file and lines	stream.c:290-292
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:290

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	56
nb uops	54
loop length	233
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.75	6.75	6.75	6.75	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.75	6.75	6.75	6.75	3.00	2.67	2.67	2.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.00
Dispatch	6.75
Overall L1	9.00

Vectorization ratios

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

2% of peak load performance is reached (2.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (3.11 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402df0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4ceb890c0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x18(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x20(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JB 402eea <main.extracted.45+0xfa>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x406060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffffc,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 402eb4 <main.extracted.45+0xc4>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA (,%RSI,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RCX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 402eb6 <main.extracted.45+0xc6>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 402eea <main.extracted.45+0xfa>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SUB %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SUB %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x4ceb890e0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.45–	0.15	0.04
○Loop 12 - stream.c:291-292 - exec	0.15	0.04
○Loop 11 - stream.c:291-292 - exec	0.00	0.00

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