OV - exec - Function main.omp

	Function: main.omp_outlined.18	Module: exec	Source: stream.c:290-292	Coverage (incl. loops): 0.15% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 290 - 292

--------------------------------------------------------------------------------

290: #pragma omp parallel for

291:     for (j = 0; j < STREAM_ARRAY_SIZE; j++)

292: 		a[j] = 2.0E0 * a[j];

0x203940 PUSH	%RBP

0x203941 MOV	%RSP,%RBP

0x203944 PUSH	%R14

0x203946 PUSH	%RBX

0x203947 SUB	$0x20,%RSP

0x20394b MOV	(%RDI),%R14D

0x20394e LEA	0x287b(%RIP),%RBX

0x203955 MOVQ	$0,-0x28(%RBP)

0x20395d MOVQ	$0x3344ffff,-0x18(%RBP)

0x203965 MOVQ	$0x1,-0x30(%RBP)

0x20396d MOVL	$0,-0x1c(%RBP)

0x203974 SUB	$0x8,%RSP

0x203978 MOV	$0x1108,%RDI

0x203982 LEA	-0x30(%RBP),%RAX

0x203986 LEA	-0x1c(%RBP),%RCX

0x20398a LEA	-0x28(%RBP),%R8

0x20398e LEA	-0x18(%RBP),%R9

0x203992 MOV	%R14D,%ESI

0x203995 MOV	$0x22,%EDX

0x20399a ADD	%RBX,%RDI

0x20399d PUSH	$0x1

0x20399f PUSH	$0x1

0x2039a1 PUSH	%RAX

0x2039a2 CALL	204fc0 <@plt_start@+0x80>

0x2039a7 ADD	$0x20,%RSP

0x2039ab MOV	-0x18(%RBP),%RCX

0x2039af MOV	$0x3344ffff,%EAX

0x2039b4 CMP	$0x3344ffff,%RCX

0x2039bb CMOVL	%RCX,%RAX

0x2039bf MOV	-0x28(%RBP),%RCX

0x2039c3 MOV	%RAX,-0x18(%RBP)

0x2039c7 CMP	%RAX,%RCX

0x2039ca JG	203ad8

0x2039d0 MOV	%RAX,%RSI

0x2039d3 SUB	%RCX,%RSI

0x2039d6 MOV	$0x1270,%RDX

0x2039e0 INC	%RSI

0x2039e3 CMP	$0x4,%RSI

0x2039e7 JB	203ab3

0x2039ed CMP	$0x20,%RSI

0x2039f1 JAE	2039fa

0x2039f3 XOR	%EDI,%EDI

0x2039f5 JMP	203a7a

0x2039fa LEA	(%RBX,%RDX,1),%R8

0x2039fe MOV	%RSI,%RDI

0x203a01 AND	$-0x20,%RDI

0x203a05 XOR	%R9D,%R9D

0x203a08 LEA	0xc0(%R8,%RCX,8),%R8

(8) 0x203a10 VMOVUPD	-0xc0(%R8,%R9,8),%ZMM0

(8) 0x203a18 VMOVUPD	-0x80(%R8,%R9,8),%ZMM1

(8) 0x203a20 VMOVUPD	-0x40(%R8,%R9,8),%ZMM2

(8) 0x203a28 VMOVUPD	(%R8,%R9,8),%ZMM3

(8) 0x203a2f VADDPD	%ZMM0,%ZMM0,%ZMM0

(8) 0x203a35 VADDPD	%ZMM1,%ZMM1,%ZMM1

(8) 0x203a3b VADDPD	%ZMM2,%ZMM2,%ZMM2

(8) 0x203a41 VADDPD	%ZMM3,%ZMM3,%ZMM3

(8) 0x203a47 VMOVUPD	%ZMM0,-0xc0(%R8,%R9,8)

(8) 0x203a4f VMOVUPD	%ZMM1,-0x80(%R8,%R9,8)

(8) 0x203a57 VMOVUPD	%ZMM2,-0x40(%R8,%R9,8)

(8) 0x203a5f VMOVUPD	%ZMM3,(%R8,%R9,8)

(8) 0x203a66 ADD	$0x20,%R9

(8) 0x203a6a CMP	%R9,%RDI

(8) 0x203a6d JNE	203a10

0x203a6f CMP	%RDI,%RSI

0x203a72 JE	203ad8

0x203a74 TEST	$0x1c,%SIL

0x203a78 JE	203ab0

0x203a7a LEA	(%RBX,%RDX,1),%R9

0x203a7e MOV	%RSI,%R8

0x203a81 AND	$-0x4,%R8

0x203a85 LEA	(%R9,%RCX,8),%R9

0x203a89 ADD	%R8,%RCX

0x203a8c NOPL	(%RAX)

(9) 0x203a90 VMOVUPD	(%R9,%RDI,8),%YMM0

(9) 0x203a96 VADDPD	%YMM0,%YMM0,%YMM0

(9) 0x203a9a VMOVUPD	%YMM0,(%R9,%RDI,8)

(9) 0x203aa0 ADD	$0x4,%RDI

(9) 0x203aa4 CMP	%RDI,%R8

(9) 0x203aa7 JNE	203a90

0x203aa9 CMP	%R8,%RSI

0x203aac JNE	203ab3

0x203aae JMP	203ad8

0x203ab0 ADD	%RDI,%RCX

0x203ab3 DEC	%RCX

0x203ab6 ADD	%RBX,%RDX

0x203ab9 NOPL	(%RAX)

(7) 0x203ac0 VMOVSD	0x8(%RDX,%RCX,8),%XMM0

(7) 0x203ac6 VADDSD	%XMM0,%XMM0,%XMM0

(7) 0x203aca VMOVSD	%XMM0,0x8(%RDX,%RCX,8)

(7) 0x203ad0 INC	%RCX

(7) 0x203ad3 CMP	%RAX,%RCX

(7) 0x203ad6 JL	203ac0

0x203ad8 MOV	$0x1120,%RAX

0x203ae2 MOV	%R14D,%ESI

0x203ae5 ADD	%RAX,%RBX

0x203ae8 MOV	%RBX,%RDI

0x203aeb VZEROUPPER

0x203aee CALL	204fe0 <@plt_start@+0xa0>

0x203af3 ADD	$0x20,%RSP

0x203af7 POP	%RBX

0x203af8 POP	%R14

0x203afa POP	%RBP

0x203afb RET

0x203afc NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►98.87+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
►1.13+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	unknown kernel region	unknown kernel region	kernel

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	stream.c:290-292
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:290-292.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.83 to 0.93 cycles (13.84x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:290

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	77
nb uops	77
loop length	304
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.83 cycles
front end	12.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.50	10.50	10.25	10.25	5.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.50	10.50	10.25	10.25	5.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.83
Dispatch	10.50
Overall L1	12.83

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

all	10%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.83 cycles. At this rate:

1% of peak load performance is reached (1.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.81 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.83 to 10.50 cycles (1.22x speedup).

ASM code

In the binary file, the address of the function is: 203940

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
LEA 0x287b(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x1108,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x1c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204fc0 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x18(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	1	0.50	N/A
MOV -0x28(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
CMP %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JG 203ad8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x1270,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMP $0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 203ab3 <main.omp_outlined.18+0x173>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
CMP $0x20,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 2039fa <main.omp_outlined.18+0xba>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 203a7a <main.omp_outlined.18+0x13a>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
LEA (%RBX,%RDX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R8,%RCX,8),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
CMP %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 203ad8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
TEST $0x1c,%SIL	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JE 203ab0 <main.omp_outlined.18+0x170>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA (%RBX,%RDX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R9,%RCX,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 203ab3 <main.omp_outlined.18+0x173>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 203ad8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
DEC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x1120,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204fe0 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	stream.c:290-292
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:290

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	77
nb uops	77
loop length	304
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.83 cycles
front end	12.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.50	10.50	10.25	10.25	5.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.50	10.50	10.25	10.25	5.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.83
Dispatch	10.50
Overall L1	12.83

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

all	10%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.83 cycles. At this rate:

1% of peak load performance is reached (1.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.81 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 203940

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
LEA 0x287b(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x1108,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x1c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204fc0 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x18(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	1	0.50	N/A
MOV -0x28(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
CMP %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JG 203ad8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x1270,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMP $0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 203ab3 <main.omp_outlined.18+0x173>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
CMP $0x20,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 2039fa <main.omp_outlined.18+0xba>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 203a7a <main.omp_outlined.18+0x13a>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
LEA (%RBX,%RDX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R8,%RCX,8),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
CMP %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 203ad8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
TEST $0x1c,%SIL	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JE 203ab0 <main.omp_outlined.18+0x170>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA (%RBX,%RDX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R9,%RCX,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 203ab3 <main.omp_outlined.18+0x173>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 203ad8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
DEC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x1120,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204fe0 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.18–	0.15	0.04
○Loop 8 - stream.c:292-292 - exec	0.15	0.04
○Loop 7 - stream.c:291-292 - exec	0.00	0.00
○Loop 9 - stream.c:292-292 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code