OV - exec - Function main._omp

	Function: main._omp_fn.7	Module: exec	Source: stream.c:354-356	Coverage (incl. loops): 27.58% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 354 - 356

--------------------------------------------------------------------------------

354: #pragma omp parallel for

355: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

356: 	    a[j] = b[j]+scalar*c[j];

0x4021a0 PUSH	%RBP

0x4021a1 MOV	$0x401060,%RAX

0x4021ab MOV	%RSP,%RBP

0x4021ae PUSH	%R14

0x4021b0 PUSH	%R13

0x4021b2 PUSH	%R12

0x4021b4 PUSH	%RBX

0x4021b5 MOV	%RDI,%RBX

0x4021b8 MOV	$0x401030,%R13

0x4021c2 AND	$-0x40,%RSP

0x4021c6 CALL	%RAX

0x4021c8 MOVSXD	%EAX,%R12

0x4021cb CALL	%R13

0x4021ce MOVSXD	%EAX,%RCX

0x4021d1 MOV	$0x33450000,%EAX

0x4021d6 CQTO

0x4021d8 IDIV	%R12

0x4021db CMP	%RDX,%RCX

0x4021de JL	4024d0

0x4021e4 IMUL	%RAX,%RCX

0x4021e8 ADD	%RCX,%RDX

0x4021eb LEA	(%RAX,%RDX,1),%R10

0x4021ef CMP	%R10,%RDX

0x4021f2 JGE	4024ad

0x4021f8 LEA	-0x1(%RAX),%RSI

0x4021fc VMOVSD	(%RBX),%XMM1

0x402200 MOV	%RDX,%RBX

0x402203 CMP	$0x6,%RSI

0x402207 JBE	4024e0

0x40220d MOV	%RAX,%R11

0x402210 LEA	(,%RDX,8),%RSI

0x402218 MOV	$0x19a687100,%R13

0x402222 MOV	$0x407100,%R14

0x40222c SHR	$0x3,%R11

0x402230 VBROADCASTSD	%XMM1,%ZMM0

0x402236 SAL	$0x6,%R11

0x40223a LEA	-0x40(%R11),%R9

0x40223e MOV	$0x334907100,%R12

0x402248 LEA	(%R13,%RSI,1),%RDI

0x40224d LEA	(%R14,%RSI,1),%R8

0x402251 SHR	$0x6,%R9

0x402255 INC	%R9

0x402258 ADD	%R12,%RSI

0x40225b XOR	%ECX,%ECX

0x40225d AND	$0x7,%R9D

0x402261 JE	402349

0x402267 CMP	$0x1,%R9

0x40226b JE	402327

0x402271 CMP	$0x2,%R9

0x402275 JE	40230e

0x40227b CMP	$0x3,%R9

0x40227f JE	4022f5

0x402281 CMP	$0x4,%R9

0x402285 JE	4022dc

0x402287 CMP	$0x5,%R9

0x40228b JE	4022c3

0x40228d CMP	$0x6,%R9

0x402291 JE	4022aa

0x402293 VMOVUPD	(%R8),%ZMM2

0x402299 MOV	$0x40,%ECX

0x40229e VFMADD213PD	(%RDI),%ZMM0,%ZMM2

0x4022a4 VMOVUPD	%ZMM2,(%RSI)

0x4022aa VMOVUPD	(%R8,%RCX,1),%ZMM3

0x4022b1 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM3

0x4022b8 VMOVUPD	%ZMM3,(%RSI,%RCX,1)

0x4022bf ADD	$0x40,%RCX

0x4022c3 VMOVUPD	(%R8,%RCX,1),%ZMM4

0x4022ca VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM4

0x4022d1 VMOVUPD	%ZMM4,(%RSI,%RCX,1)

0x4022d8 ADD	$0x40,%RCX

0x4022dc VMOVUPD	(%R8,%RCX,1),%ZMM5

0x4022e3 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM5

0x4022ea VMOVUPD	%ZMM5,(%RSI,%RCX,1)

0x4022f1 ADD	$0x40,%RCX

0x4022f5 VMOVUPD	(%R8,%RCX,1),%ZMM6

0x4022fc VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM6

0x402303 VMOVUPD	%ZMM6,(%RSI,%RCX,1)

0x40230a ADD	$0x40,%RCX

0x40230e VMOVUPD	(%R8,%RCX,1),%ZMM7

0x402315 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM7

0x40231c VMOVUPD	%ZMM7,(%RSI,%RCX,1)

0x402323 ADD	$0x40,%RCX

0x402327 VMOVUPD	(%R8,%RCX,1),%ZMM8

0x40232e VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM8

0x402335 VMOVUPD	%ZMM8,(%RSI,%RCX,1)

0x40233c ADD	$0x40,%RCX

0x402340 CMP	%R11,%RCX

0x402343 JE	402416

(2) 0x402349 VMOVUPD	(%R8,%RCX,1),%ZMM9

(2) 0x402350 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM9

(2) 0x402357 VMOVUPD	%ZMM9,(%RSI,%RCX,1)

(2) 0x40235e VMOVUPD	0x40(%R8,%RCX,1),%ZMM10

(2) 0x402366 VFMADD213PD	0x40(%RDI,%RCX,1),%ZMM0,%ZMM10

(2) 0x40236e VMOVUPD	%ZMM10,0x40(%RSI,%RCX,1)

(2) 0x402376 VMOVUPD	0x80(%R8,%RCX,1),%ZMM11

(2) 0x40237e VFMADD213PD	0x80(%RDI,%RCX,1),%ZMM0,%ZMM11

(2) 0x402386 VMOVUPD	%ZMM11,0x80(%RSI,%RCX,1)

(2) 0x40238e VMOVUPD	0xc0(%R8,%RCX,1),%ZMM12

(2) 0x402396 VFMADD213PD	0xc0(%RDI,%RCX,1),%ZMM0,%ZMM12

(2) 0x40239e VMOVUPD	%ZMM12,0xc0(%RSI,%RCX,1)

(2) 0x4023a6 VMOVUPD	0x100(%R8,%RCX,1),%ZMM13

(2) 0x4023ae VFMADD213PD	0x100(%RDI,%RCX,1),%ZMM0,%ZMM13

(2) 0x4023b6 VMOVUPD	%ZMM13,0x100(%RSI,%RCX,1)

(2) 0x4023be VMOVUPD	0x140(%R8,%RCX,1),%ZMM14

(2) 0x4023c6 VFMADD213PD	0x140(%RDI,%RCX,1),%ZMM0,%ZMM14

(2) 0x4023ce VMOVUPD	%ZMM14,0x140(%RSI,%RCX,1)

(2) 0x4023d6 VMOVUPD	0x180(%R8,%RCX,1),%ZMM15

(2) 0x4023de VFMADD213PD	0x180(%RDI,%RCX,1),%ZMM0,%ZMM15

(2) 0x4023e6 VMOVUPD	%ZMM15,0x180(%RSI,%RCX,1)

(2) 0x4023ee VMOVUPD	0x1c0(%R8,%RCX,1),%ZMM2

(2) 0x4023f6 VFMADD213PD	0x1c0(%RDI,%RCX,1),%ZMM0,%ZMM2

(2) 0x4023fe VMOVUPD	%ZMM2,0x1c0(%RSI,%RCX,1)

(2) 0x402406 ADD	$0x200,%RCX

(2) 0x40240d CMP	%R11,%RCX

(2) 0x402410 JNE	402349

0x402416 MOV	%RAX,%RDI

0x402419 AND	$-0x8,%RDI

0x40241d ADD	%RDI,%RDX

0x402420 CMP	%RDI,%RAX

0x402423 JE	4024c0

0x402429 SUB	%RDI,%RAX

0x40242c LEA	-0x1(%RAX),%RSI

0x402430 CMP	$0x2,%RSI

0x402434 JBE	40245f

0x402436 ADD	%RBX,%RDI

0x402439 MOV	%RAX,%RBX

0x40243c VBROADCASTSD	%XMM1,%YMM0

0x402441 AND	$-0x4,%RBX

0x402445 VMOVUPD	(%R13,%RDI,8),%YMM3

0x40244c VFMADD132PD	(%R14,%RDI,8),%YMM3,%YMM0

0x402452 VMOVUPD	%YMM0,(%R12,%RDI,8)

0x402458 ADD	%RBX,%RDX

0x40245b TEST	$0x3,%AL

0x40245d JE	4024c0

0x40245f LEA	0x1(%RDX),%RAX

0x402463 VMOVSD	(%R14,%RDX,8),%XMM4

0x402469 VFMADD213SD	(%R13,%RDX,8),%XMM1,%XMM4

0x402470 VMOVSD	%XMM4,(%R12,%RDX,8)

0x402476 CMP	%RAX,%R10

0x402479 JLE	4024c0

0x40247b ADD	$0x2,%RDX

0x40247f VMOVSD	(%R14,%RAX,8),%XMM5

0x402485 VFMADD213SD	(%R13,%RAX,8),%XMM1,%XMM5

0x40248c VMOVSD	%XMM5,(%R12,%RAX,8)

0x402492 CMP	%RDX,%R10

0x402495 JLE	4024c0

0x402497 VMOVSD	(%R13,%RDX,8),%XMM6

0x40249e VFMADD132SD	(%R14,%RDX,8),%XMM6,%XMM1

0x4024a4 VMOVSD	%XMM1,(%R12,%RDX,8)

0x4024aa VZEROUPPER

0x4024ad LEA	-0x20(%RBP),%RSP

0x4024b1 POP	%RBX

0x4024b2 POP	%R12

0x4024b4 POP	%R13

0x4024b6 POP	%R14

0x4024b8 POP	%RBP

0x4024b9 RET

0x4024ba NOPW	(%RAX,%RAX,1)

0x4024c0 VZEROUPPER

0x4024c3 LEA	-0x20(%RBP),%RSP

0x4024c7 POP	%RBX

0x4024c8 POP	%R12

0x4024ca POP	%R13

0x4024cc POP	%R14

0x4024ce POP	%RBP

0x4024cf RET

0x4024d0 INC	%RAX

0x4024d3 XOR	%EDX,%EDX

0x4024d5 JMP	4021e4

0x4024da NOPW	(%RAX,%RAX,1)

0x4024e0 XOR	%EDI,%EDI

0x4024e2 MOV	$0x19a687100,%R13

0x4024ec MOV	$0x407100,%R14

0x4024f6 MOV	$0x334907100,%R12

0x402500 JMP	402429

0x402505 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○98.94	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.06	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:354-356
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:354-356.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.83 to 16.00 cycles (1.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.83 to 20.45 cycles (1.26x speedup).

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

69% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
72% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 63 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:354
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:354
VMOVUPD: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time). 7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 126 FP arithmetical operations:

63: addition or subtraction (all inside FMA instructions)
63: multiply (all inside FMA instructions)

The binary function is loading 1016 bytes (127 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	149
nb uops	155
loop length	675
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	8
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.83 cycles
front end	25.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	18.00	18.00	18.00	18.00	12.00	12.00	12.00	12.00	6.00	5.50	1.50	0.00	9.00	9.00
cycles	18.00	18.00	18.00	18.00	12.00	16.67	16.67	16.67	10.00	8.50	1.50	0.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	25.83
Dispatch	18.00
DIV/SQRT	7.00-12.00
Overall L1	25.83

Vectorization ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	66%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	72%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	44%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	72%
div/sqrt	0%
other	9%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	66%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	71%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	46%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	71%
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.83 cycles. At this rate:

40% of peak load performance is reached (39.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (19.51 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.83 to 18.00 cycles (1.44x speedup).

ASM code

In the binary file, the address of the function is: 4021a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x401030,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL %R13	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %R12	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 4024d0 <main._omp_fn.7+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 4024ad <main._omp_fn.7+0x30d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RBX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 4024e0 <main._omp_fn.7+0x340>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x19a687100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x407100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x3,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
SAL $0x6,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x40(%R11),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334907100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R13,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R14,%RSI,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x7,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 402349 <main._omp_fn.7+0x1a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402327 <main._omp_fn.7+0x187>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40230e <main._omp_fn.7+0x16e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022f5 <main._omp_fn.7+0x155>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022dc <main._omp_fn.7+0x13c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022c3 <main._omp_fn.7+0x123>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022aa <main._omp_fn.7+0x10a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R8),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
MOV $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213PD (%RDI),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM2,(%RSI)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
VMOVUPD (%R8,%RCX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM6,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM8,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402416 <main._omp_fn.7+0x276>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4024c0 <main._omp_fn.7+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 40245f <main._omp_fn.7+0x2bf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
AND $-0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R13,%RDI,8),%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD (%R14,%RDI,8),%YMM3,%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM0,(%R12,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (50.0%)
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TEST $0x3,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 4024c0 <main._omp_fn.7+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R14,%RDX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%R13,%RDX,8),%XMM1,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 4024c0 <main._omp_fn.7+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R14,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%R13,%RAX,8),%XMM1,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,(%R12,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 4024c0 <main._omp_fn.7+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R13,%RDX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD132SD (%R14,%RDX,8),%XMM6,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4021e4 <main._omp_fn.7+0x44>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x19a687100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x407100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334907100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 402429 <main._omp_fn.7+0x289>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:354-356
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

69% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
72% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 63 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:354
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:354
VMOVUPD: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:356

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 126 FP arithmetical operations:

63: addition or subtraction (all inside FMA instructions)
63: multiply (all inside FMA instructions)

The binary function is loading 1016 bytes (127 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	149
nb uops	155
loop length	675
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	8
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.83 cycles
front end	25.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	18.00	18.00	18.00	18.00	12.00	12.00	12.00	12.00	6.00	5.50	1.50	0.00	9.00	9.00
cycles	18.00	18.00	18.00	18.00	12.00	16.67	16.67	16.67	10.00	8.50	1.50	0.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	25.83
Dispatch	18.00
DIV/SQRT	7.00-12.00
Overall L1	25.83

Vectorization ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	66%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	72%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	44%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	72%
div/sqrt	0%
other	9%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	66%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	71%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	46%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	71%
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.83 cycles. At this rate:

40% of peak load performance is reached (39.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (19.51 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4021a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x401030,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL %R13	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %R12	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 4024d0 <main._omp_fn.7+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 4024ad <main._omp_fn.7+0x30d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RBX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 4024e0 <main._omp_fn.7+0x340>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x19a687100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x407100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x3,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
SAL $0x6,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x40(%R11),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334907100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R13,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R14,%RSI,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x7,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 402349 <main._omp_fn.7+0x1a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402327 <main._omp_fn.7+0x187>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40230e <main._omp_fn.7+0x16e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022f5 <main._omp_fn.7+0x155>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022dc <main._omp_fn.7+0x13c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022c3 <main._omp_fn.7+0x123>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4022aa <main._omp_fn.7+0x10a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R8),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
MOV $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213PD (%RDI),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM2,(%RSI)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
VMOVUPD (%R8,%RCX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM6,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM8,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402416 <main._omp_fn.7+0x276>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4024c0 <main._omp_fn.7+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 40245f <main._omp_fn.7+0x2bf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
AND $-0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R13,%RDI,8),%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD (%R14,%RDI,8),%YMM3,%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM0,(%R12,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (50.0%)
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TEST $0x3,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 4024c0 <main._omp_fn.7+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R14,%RDX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%R13,%RDX,8),%XMM1,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 4024c0 <main._omp_fn.7+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R14,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%R13,%RAX,8),%XMM1,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,(%R12,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 4024c0 <main._omp_fn.7+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R13,%RDX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD132SD (%R14,%RDX,8),%XMM6,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4021e4 <main._omp_fn.7+0x44>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x19a687100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x407100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334907100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 402429 <main._omp_fn.7+0x289>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.7–	27.58	7.45
○Loop 2 - stream.c:356-356 - exec	27.58	7.27

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