OV - exec - Function main.omp

	Function: main.omp_outlined.31	Module: exec	Source: stream.c:342-344	Coverage (incl. loops): 29.41% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 342 - 344

--------------------------------------------------------------------------------

342: #pragma omp parallel for

343: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

344: 	    c[j] = a[j]+b[j];

0x203d40 PUSH	%RBP

0x203d41 MOV	%RSP,%RBP

0x203d44 PUSH	%R15

0x203d46 PUSH	%R14

0x203d48 PUSH	%R13

0x203d4a PUSH	%R12

0x203d4c PUSH	%RBX

0x203d4d SUB	$0x28,%RSP

0x203d51 MOV	(%RDI),%R14D

0x203d54 LEA	0x31ad(%RIP),%RBX

0x203d5b MOVQ	$0,-0x40(%RBP)

0x203d63 MOVQ	$0x3344ffff,-0x30(%RBP)

0x203d6b MOVQ	$0x1,-0x48(%RBP)

0x203d73 MOVL	$0,-0x34(%RBP)

0x203d7a SUB	$0x8,%RSP

0x203d7e MOV	$0x11e0,%RDI

0x203d88 LEA	-0x48(%RBP),%RAX

0x203d8c LEA	-0x40(%RBP),%R8

0x203d90 LEA	-0x34(%RBP),%RCX

0x203d94 LEA	-0x30(%RBP),%R9

0x203d98 MOV	%R14D,%ESI

0x203d9b MOV	$0x22,%EDX

0x203da0 ADD	%RBX,%RDI

0x203da3 PUSH	$0x1

0x203da5 PUSH	$0x1

0x203da7 PUSH	%RAX

0x203da8 CALL	204d00 <@plt_start@+0x80>

0x203dad ADD	$0x20,%RSP

0x203db1 MOV	-0x30(%RBP),%RCX

0x203db5 MOV	-0x40(%RBP),%R8

0x203db9 MOV	$0x3344ffff,%EAX

0x203dbe CMP	$0x3344ffff,%RCX

0x203dc5 CMOVL	%RCX,%RAX

0x203dc9 MOV	%RAX,-0x30(%RBP)

0x203dcd CMP	%RAX,%R8

0x203dd0 JG	203f3d

0x203dd6 MOV	%RAX,%RDI

0x203dd9 SUB	%R8,%RDI

0x203ddc MOV	$0x1278,%RCX

0x203de6 MOV	$0x19a281278,%RDX

0x203df0 MOV	$0x334501278,%RSI

0x203dfa INC	%RDI

0x203dfd CMP	$0x4,%RDI

0x203e01 JAE	203e0b

0x203e03 MOV	%R8,%R10

0x203e06 JMP	203f10

0x203e0b CMP	$0x20,%RDI

0x203e0f JAE	203e19

0x203e11 XOR	%R9D,%R9D

0x203e14 JMP	203ec9

0x203e19 LEA	(%RBX,%RCX,1),%R10

0x203e1d LEA	(%RBX,%RDX,1),%R11

0x203e21 LEA	(%RBX,%RSI,1),%R15

0x203e25 MOV	%RDI,%R9

0x203e28 AND	$-0x20,%R9

0x203e2c XOR	%R12D,%R12D

0x203e2f LEA	0xc0(%R10,%R8,8),%R10

0x203e37 LEA	0xc0(%R11,%R8,8),%R11

0x203e3f LEA	0xc0(%R15,%R8,8),%R15

0x203e47 NOPW	(%RAX,%RAX,1)

(13) 0x203e50 VMOVUPD	-0xc0(%R10,%R12,8),%ZMM0

(13) 0x203e58 VMOVUPD	-0x80(%R10,%R12,8),%ZMM1

(13) 0x203e60 VMOVUPD	-0x40(%R10,%R12,8),%ZMM2

(13) 0x203e68 VMOVUPD	(%R10,%R12,8),%ZMM3

(13) 0x203e6f VADDPD	-0xc0(%R11,%R12,8),%ZMM0,%ZMM0

(13) 0x203e77 VADDPD	-0x80(%R11,%R12,8),%ZMM1,%ZMM1

(13) 0x203e7f VADDPD	-0x40(%R11,%R12,8),%ZMM2,%ZMM2

(13) 0x203e87 VADDPD	(%R11,%R12,8),%ZMM3,%ZMM3

(13) 0x203e8e VMOVUPD	%ZMM0,-0xc0(%R15,%R12,8)

(13) 0x203e96 VMOVUPD	%ZMM1,-0x80(%R15,%R12,8)

(13) 0x203e9e VMOVUPD	%ZMM2,-0x40(%R15,%R12,8)

(13) 0x203ea6 VMOVUPD	%ZMM3,(%R15,%R12,8)

(13) 0x203ead ADD	$0x20,%R12

(13) 0x203eb1 CMP	%R12,%R9

(13) 0x203eb4 JNE	203e50

0x203eb6 CMP	%R9,%RDI

0x203eb9 JE	203f3d

0x203ebf TEST	$0x1c,%DIL

0x203ec3 JE	203f67

0x203ec9 MOV	%RDI,%R11

0x203ecc LEA	(%RBX,%RCX,1),%R15

0x203ed0 LEA	(%RBX,%RDX,1),%R12

0x203ed4 AND	$-0x4,%R11

0x203ed8 LEA	(%RBX,%RSI,1),%R13

0x203edc LEA	(%R8,%R11,1),%R10

0x203ee0 LEA	(%R15,%R8,8),%R15

0x203ee4 LEA	(%R12,%R8,8),%R12

0x203ee8 LEA	(%R13,%R8,8),%R8

0x203eed NOPL	(%RAX)

(15) 0x203ef0 VMOVUPD	(%R15,%R9,8),%YMM0

(15) 0x203ef6 VADDPD	(%R12,%R9,8),%YMM0,%YMM0

(15) 0x203efc VMOVUPD	%YMM0,(%R8,%R9,8)

(15) 0x203f02 ADD	$0x4,%R9

(15) 0x203f06 CMP	%R9,%R11

(15) 0x203f09 JNE	203ef0

0x203f0b CMP	%R11,%RDI

0x203f0e JE	203f3d

0x203f10 DEC	%R10

0x203f13 ADD	%RBX,%RCX

0x203f16 ADD	%RBX,%RDX

0x203f19 ADD	%RBX,%RSI

0x203f1c NOPL	(%RAX)

(14) 0x203f20 VMOVSD	0x8(%RCX,%R10,8),%XMM0

(14) 0x203f27 VADDSD	0x8(%RDX,%R10,8),%XMM0,%XMM0

(14) 0x203f2e VMOVSD	%XMM0,0x8(%RSI,%R10,8)

(14) 0x203f35 INC	%R10

(14) 0x203f38 CMP	%RAX,%R10

(14) 0x203f3b JL	203f20

0x203f3d MOV	$0x11f8,%RAX

0x203f47 MOV	%R14D,%ESI

0x203f4a ADD	%RAX,%RBX

0x203f4d MOV	%RBX,%RDI

0x203f50 VZEROUPPER

0x203f53 CALL	204d20 <@plt_start@+0xa0>

0x203f58 ADD	$0x28,%RSP

0x203f5c POP	%RBX

0x203f5d POP	%R12

0x203f5f POP	%R13

0x203f61 POP	%R14

0x203f63 POP	%R15

0x203f65 POP	%RBP

0x203f66 RET

0x203f67 ADD	%R9,%R8

0x203f6a JMP	203e03

0x203f6f NOP

Coverage (%)	Name	Source Location	Module
►99.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:342-344
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342-344.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.50 to 1.18 cycles (14.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	98
nb uops	99
loop length	402
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	13.50	13.50	13.50	13.50	6.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	13.50	13.50	13.50	13.50	6.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.50
Dispatch	13.50
Overall L1	16.50

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.50 cycles. At this rate:

1% of peak load performance is reached (1.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.18 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.50 to 13.50 cycles (1.22x speedup).

ASM code

In the binary file, the address of the function is: 203d40

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
LEA 0x31ad(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x11e0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204d00 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	1	0.50	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
CMP %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JG 203f3d <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x1278,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a281278,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334501278,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x4,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 203e0b <main.omp_outlined.31+0xcb>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 203f10 <main.omp_outlined.31+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
CMP $0x20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 203e19 <main.omp_outlined.31+0xd9>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 203ec9 <main.omp_outlined.31+0x189>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
LEA (%RBX,%RCX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R10,%R8,8),%R10	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA 0xc0(%R11,%R8,8),%R11	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA 0xc0(%R15,%R8,8),%R15	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 203f3d <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
TEST $0x1c,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JE 203f67 <main.omp_outlined.31+0x227>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RCX,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
AND $-0x4,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R8,%R11,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R15,%R8,8),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R12,%R8,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R13,%R8,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R11,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 203f3d <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
DEC %R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x11f8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204d20 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
ADD %R9,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JMP 203e03 <main.omp_outlined.31+0xc3>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:342-344
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:342

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	98
nb uops	99
loop length	402
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	13.50	13.50	13.50	13.50	6.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	13.50	13.50	13.50	13.50	6.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.50
Dispatch	13.50
Overall L1	16.50

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.50 cycles. At this rate:

1% of peak load performance is reached (1.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.18 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 203d40

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
LEA 0x31ad(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x11e0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204d00 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	1	0.50	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
CMP %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JG 203f3d <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x1278,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a281278,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334501278,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x4,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 203e0b <main.omp_outlined.31+0xcb>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 203f10 <main.omp_outlined.31+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
CMP $0x20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 203e19 <main.omp_outlined.31+0xd9>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 203ec9 <main.omp_outlined.31+0x189>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
LEA (%RBX,%RCX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R10,%R8,8),%R10	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA 0xc0(%R11,%R8,8),%R11	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA 0xc0(%R15,%R8,8),%R15	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 203f3d <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
TEST $0x1c,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JE 203f67 <main.omp_outlined.31+0x227>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RCX,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
AND $-0x4,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R8,%R11,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R15,%R8,8),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R12,%R8,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R13,%R8,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R11,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 203f3d <main.omp_outlined.31+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
DEC %R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x11f8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204d20 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
ADD %R9,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JMP 203e03 <main.omp_outlined.31+0xc3>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.31–	29.41	7.53
○Loop 13 - stream.c:344-344 - exec	29.41	7.33
○Loop 14 - stream.c:343-344 - exec	0.00	0.00
○Loop 15 - stream.c:344-344 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code