OV - exec - Function main.omp

	Function: main.omp_outlined.29	Module: exec	Source: stream.c:330-332	Coverage (incl. loops): 22.11% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c: 330 - 332

--------------------------------------------------------------------------------

330: #pragma omp parallel for

331: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

332: 	    b[j] = scalar*c[j];

0x203b40 PUSH	%RBP

0x203b41 MOV	%RSP,%RBP

0x203b44 PUSH	%R15

0x203b46 PUSH	%R14

0x203b48 PUSH	%RBX

0x203b49 SUB	$0x28,%RSP

0x203b4d MOV	(%RDI),%R14D

0x203b50 LEA	0x33b1(%RIP),%RBX

0x203b57 MOV	%RDX,%R15

0x203b5a MOVQ	$0,-0x30(%RBP)

0x203b62 MOVQ	$0x3344ffff,-0x20(%RBP)

0x203b6a MOVQ	$0x1,-0x38(%RBP)

0x203b72 MOVL	$0,-0x24(%RBP)

0x203b79 SUB	$0x8,%RSP

0x203b7d MOV	$0x1198,%RDI

0x203b87 LEA	-0x38(%RBP),%RAX

0x203b8b LEA	-0x24(%RBP),%RCX

0x203b8f LEA	-0x30(%RBP),%R8

0x203b93 LEA	-0x20(%RBP),%R9

0x203b97 MOV	%R14D,%ESI

0x203b9a MOV	$0x22,%EDX

0x203b9f ADD	%RBX,%RDI

0x203ba2 PUSH	$0x1

0x203ba4 PUSH	$0x1

0x203ba6 PUSH	%RAX

0x203ba7 CALL	204d00 <@plt_start@+0x80>

0x203bac ADD	$0x20,%RSP

0x203bb0 MOV	-0x20(%RBP),%RCX

0x203bb4 MOV	-0x30(%RBP),%RDI

0x203bb8 MOV	$0x3344ffff,%EAX

0x203bbd CMP	$0x3344ffff,%RCX

0x203bc4 CMOVL	%RCX,%RAX

0x203bc8 MOV	%RAX,-0x20(%RBP)

0x203bcc CMP	%RAX,%RDI

0x203bcf JG	203d06

0x203bd5 VMOVSD	(%R15),%XMM0

0x203bda MOV	%RAX,%RSI

0x203bdd SUB	%RDI,%RSI

0x203be0 MOV	$0x334501278,%RCX

0x203bea MOV	$0x19a281278,%RDX

0x203bf4 INC	%RSI

0x203bf7 CMP	$0x4,%RSI

0x203bfb JAE	203c05

0x203bfd MOV	%RDI,%R9

0x203c00 JMP	203cda

0x203c05 CMP	$0x20,%RSI

0x203c09 JAE	203c13

0x203c0b XOR	%R8D,%R8D

0x203c0e JMP	203c96

0x203c13 LEA	(%RBX,%RCX,1),%R9

0x203c17 LEA	(%RBX,%RDX,1),%R10

0x203c1b VBROADCASTSD	%XMM0,%ZMM1

0x203c21 MOV	%RSI,%R8

0x203c24 AND	$-0x20,%R8

0x203c28 XOR	%R11D,%R11D

0x203c2b LEA	0xc0(%R9,%RDI,8),%R9

0x203c33 LEA	0xc0(%R10,%RDI,8),%R10

0x203c3b NOPL	(%RAX,%RAX,1)

(10) 0x203c40 VMULPD	-0xc0(%R9,%R11,8),%ZMM1,%ZMM2

(10) 0x203c48 VMULPD	-0x80(%R9,%R11,8),%ZMM1,%ZMM3

(10) 0x203c50 VMULPD	-0x40(%R9,%R11,8),%ZMM1,%ZMM4

(10) 0x203c58 VMULPD	(%R9,%R11,8),%ZMM1,%ZMM5

(10) 0x203c5f VMOVUPD	%ZMM2,-0xc0(%R10,%R11,8)

(10) 0x203c67 VMOVUPD	%ZMM3,-0x80(%R10,%R11,8)

(10) 0x203c6f VMOVUPD	%ZMM4,-0x40(%R10,%R11,8)

(10) 0x203c77 VMOVUPD	%ZMM5,(%R10,%R11,8)

(10) 0x203c7e ADD	$0x20,%R11

(10) 0x203c82 CMP	%R11,%R8

(10) 0x203c85 JNE	203c40

0x203c87 CMP	%R8,%RSI

0x203c8a JE	203d06

0x203c8c TEST	$0x1c,%SIL

0x203c90 JE	203d2c

0x203c96 MOV	%RSI,%R10

0x203c99 LEA	(%RBX,%RCX,1),%R11

0x203c9d AND	$-0x4,%R10

0x203ca1 LEA	(%RBX,%RDX,1),%R15

0x203ca5 VBROADCASTSD	%XMM0,%YMM1

0x203caa LEA	(%RDI,%R10,1),%R9

0x203cae LEA	(%R11,%RDI,8),%R11

0x203cb2 LEA	(%R15,%RDI,8),%RDI

0x203cb6 NOPW	%CS:(%RAX,%RAX,1)

(12) 0x203cc0 VMULPD	(%R11,%R8,8),%YMM1,%YMM2

(12) 0x203cc6 VMOVUPD	%YMM2,(%RDI,%R8,8)

(12) 0x203ccc ADD	$0x4,%R8

(12) 0x203cd0 CMP	%R8,%R10

(12) 0x203cd3 JNE	203cc0

0x203cd5 CMP	%R10,%RSI

0x203cd8 JE	203d06

0x203cda DEC	%R9

0x203cdd ADD	%RBX,%RCX

0x203ce0 ADD	%RBX,%RDX

0x203ce3 NOPW	%CS:(%RAX,%RAX,1)

(11) 0x203cf0 VMULSD	0x8(%RCX,%R9,8),%XMM0,%XMM1

(11) 0x203cf7 VMOVSD	%XMM1,0x8(%RDX,%R9,8)

(11) 0x203cfe INC	%R9

(11) 0x203d01 CMP	%RAX,%R9

(11) 0x203d04 JL	203cf0

0x203d06 MOV	$0x11b0,%RAX

0x203d10 MOV	%R14D,%ESI

0x203d13 ADD	%RAX,%RBX

0x203d16 MOV	%RBX,%RDI

0x203d19 VZEROUPPER

0x203d1c CALL	204d20 <@plt_start@+0xa0>

0x203d21 ADD	$0x28,%RSP

0x203d25 POP	%RBX

0x203d26 POP	%R14

0x203d28 POP	%R15

0x203d2a POP	%RBP

0x203d2b RET

0x203d2c ADD	%R8,%RDI

0x203d2f JMP	203bfd

0x203d34 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►99.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:330-332
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:330-332.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.33 to 3.17 cycles (4.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.33 to 1.16 cycles (13.26x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:330
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:330

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:331
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:331

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	92
nb uops	92
loop length	398
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	1
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.00	12.00	12.00	12.00	6.00	4.33	4.33	4.33	0.00	1.00	1.00	0.00	0.00	0.00
cycles	12.00	12.00	12.00	12.00	6.00	4.33	4.33	4.33	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.33
Dispatch	12.00
Overall L1	15.33

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	9%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.33 cycles. At this rate:

1% of peak load performance is reached (1.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.35 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.33 to 12.00 cycles (1.28x speedup).

ASM code

In the binary file, the address of the function is: 203b40

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (6.3%)
LEA 0x33b1(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x1198,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x24(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204d00 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x20(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50	N/A
MOV %RAX,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
CMP %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JG 203d06 <main.omp_outlined.29+0x1c6>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R15),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x334501278,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a281278,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP $0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 203c05 <main.omp_outlined.29+0xc5>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 203cda <main.omp_outlined.29+0x19a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
CMP $0x20,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 203c13 <main.omp_outlined.29+0xd3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 203c96 <main.omp_outlined.29+0x156>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
LEA (%RBX,%RCX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R9,%RDI,8),%R9	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
LEA 0xc0(%R10,%RDI,8),%R10	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203d06 <main.omp_outlined.29+0x1c6>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%SIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 203d2c <main.omp_outlined.29+0x1ec>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RCX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
AND $-0x4,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM0,%YMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%RDI,%R10,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RDI,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R15,%RDI,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R10,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203d06 <main.omp_outlined.29+0x1c6>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
DEC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x11b0,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204d20 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
ADD %R8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JMP 203bfd <main.omp_outlined.29+0xbd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:330-332
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.33 to 3.17 cycles (4.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:330
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:330

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:331
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz16.benchmarkcenter.megware.com/177-374-0958/stream/build/stream/src/stream.c:331

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	92
nb uops	92
loop length	398
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	1
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.00	12.00	12.00	12.00	6.00	4.33	4.33	4.33	0.00	1.00	1.00	0.00	0.00	0.00
cycles	12.00	12.00	12.00	12.00	6.00	4.33	4.33	4.33	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.33
Dispatch	12.00
Overall L1	15.33

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	9%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.33 cycles. At this rate:

1% of peak load performance is reached (1.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.35 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 203b40

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	scal (6.3%)
LEA 0x33b1(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x1198,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x24(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204d00 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x20(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50	N/A
MOV %RAX,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (12.5%)
CMP %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JG 203d06 <main.omp_outlined.29+0x1c6>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R15),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x334501278,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a281278,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP $0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 203c05 <main.omp_outlined.29+0xc5>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 203cda <main.omp_outlined.29+0x19a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
CMP $0x20,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 203c13 <main.omp_outlined.29+0xd3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 203c96 <main.omp_outlined.29+0x156>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
LEA (%RBX,%RCX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R9,%RDI,8),%R9	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
LEA 0xc0(%R10,%RDI,8),%R10	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203d06 <main.omp_outlined.29+0x1c6>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%SIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 203d2c <main.omp_outlined.29+0x1ec>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RCX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
AND $-0x4,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM0,%YMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%RDI,%R10,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RDI,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA (%R15,%RDI,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R10,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 203d06 <main.omp_outlined.29+0x1c6>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1	N/A
DEC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x11b0,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204d20 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
ADD %R8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JMP 203bfd <main.omp_outlined.29+0xbd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.29–	22.11	5.66
○Loop 10 - stream.c:332-332 - exec	22.11	5.51
○Loop 11 - stream.c:331-332 - exec	0.00	0.00
○Loop 12 - stream.c:332-332 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code