OV - exec - Function main.omp

	Function: main.omp_outlined.14	Module: exec	Source: stream.c:271-275	Coverage (incl. loops): 0.38% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 271 - 275

--------------------------------------------------------------------------------

271: #pragma omp parallel for

272:     for (j=0; j<STREAM_ARRAY_SIZE; j++) {

273: 	    a[j] = 1.0;

274: 	    b[j] = 2.0;

275: 	    c[j] = 0.0;

0x203170 PUSH	%RBP

0x203171 MOV	%RSP,%RBP

0x203174 PUSH	%R15

0x203176 PUSH	%R14

0x203178 PUSH	%R13

0x20317a PUSH	%R12

0x20317c PUSH	%RBX

0x20317d SUB	$0x28,%RSP

0x203181 MOV	(%RDI),%R14D

0x203184 LEA	0x33a5(%RIP),%RBX

0x20318b MOVQ	$0,-0x40(%RBP)

0x203193 MOVQ	$0x3344ffff,-0x30(%RBP)

0x20319b MOVQ	$0x1,-0x48(%RBP)

0x2031a3 MOVL	$0,-0x34(%RBP)

0x2031aa SUB	$0x8,%RSP

0x2031ae MOV	$0x10b8,%RDI

0x2031b8 LEA	-0x48(%RBP),%RAX

0x2031bc LEA	-0x34(%RBP),%RCX

0x2031c0 LEA	-0x40(%RBP),%R8

0x2031c4 LEA	-0x30(%RBP),%R9

0x2031c8 MOV	%R14D,%ESI

0x2031cb MOV	$0x22,%EDX

0x2031d0 ADD	%RBX,%RDI

0x2031d3 PUSH	$0x1

0x2031d5 PUSH	$0x1

0x2031d7 PUSH	%RAX

0x2031d8 CALL	204330 <@plt_start@+0x80>

0x2031dd ADD	$0x20,%RSP

0x2031e1 MOV	-0x30(%RBP),%RAX

0x2031e5 MOV	-0x40(%RBP),%R13

0x2031e9 MOV	$0x3344ffff,%R15D

0x2031ef CMP	$0x3344ffff,%RAX

0x2031f5 CMOVL	%RAX,%R15

0x2031f9 MOV	%R15,-0x30(%RBP)

0x2031fd CMP	%R15,%R13

0x203200 JG	203322

0x203206 MOV	$0x334501190,%RAX

0x203210 MOV	%R15,%R12

0x203213 SUB	%R13,%R12

0x203216 XOR	%ESI,%ESI

0x203218 ADD	%RBX,%RAX

0x20321b LEA	0x8(,%R12,8),%RDX

0x203223 INC	%R12

0x203226 LEA	(%RAX,%R13,8),%RDI

0x20322a CALL	204340 <@plt_start@+0x90>

0x20322f MOV	$0x1190,%RAX

0x203239 MOV	$0x19a281190,%RCX

0x203243 CMP	$0x8,%R12

0x203247 JAE	203251

0x203249 MOV	%R13,%RDX

0x20324c JMP	2032e4

0x203251 MOV	$-0x5d58,%R10

0x20325b LEA	(%RBX,%RAX,1),%RDX

0x20325f MOV	%R12,%RSI

0x203262 AND	$-0x8,%RSI

0x203266 XOR	%R9D,%R9D

0x203269 VMOVDDUP	(%RBX,%R10,1),%XMM0

0x20326f MOV	$-0x5d78,%R10

0x203279 LEA	0x30(%RDX,%R13,8),%RDI

0x20327e LEA	(%RBX,%RCX,1),%RDX

0x203282 VMOVDDUP	(%RBX,%R10,1),%XMM1

0x203288 LEA	0x30(%RDX,%R13,8),%R8

0x20328d LEA	(%R13,%RSI,1),%RDX

0x203292 NOPW	%CS:(%RAX,%RAX,1)

(4) 0x2032a0 VMOVUPS	%XMM0,-0x30(%RDI,%R9,8)

(4) 0x2032a7 VMOVUPS	%XMM0,-0x20(%RDI,%R9,8)

(4) 0x2032ae VMOVUPS	%XMM0,-0x10(%RDI,%R9,8)

(4) 0x2032b5 VMOVUPS	%XMM1,-0x30(%R8,%R9,8)

(4) 0x2032bc VMOVUPS	%XMM1,-0x20(%R8,%R9,8)

(4) 0x2032c3 VMOVUPS	%XMM1,-0x10(%R8,%R9,8)

(4) 0x2032ca VMOVUPS	%XMM0,(%RDI,%R9,8)

(4) 0x2032d0 VMOVUPS	%XMM1,(%R8,%R9,8)

(4) 0x2032d6 ADD	$0x8,%R9

(4) 0x2032da CMP	%R9,%RSI

(4) 0x2032dd JNE	2032a0

0x2032df CMP	%RSI,%R12

0x2032e2 JE	203322

0x2032e4 DEC	%RDX

0x2032e7 ADD	%RBX,%RAX

0x2032ea MOV	$0x3ff0000000000000,%RSI

0x2032f4 ADD	%RBX,%RCX

0x2032f7 MOV	$0x4000000000000000,%RDI

0x203301 NOPW	%CS:(%RAX,%RAX,1)

(5) 0x203310 MOV	%RSI,0x8(%RAX,%RDX,8)

(5) 0x203315 MOV	%RDI,0x8(%RCX,%RDX,8)

(5) 0x20331a INC	%RDX

(5) 0x20331d CMP	%R15,%RDX

(5) 0x203320 JL	203310

0x203322 MOV	$0x10d0,%RAX

0x20332c MOV	%R14D,%ESI

0x20332f ADD	%RAX,%RBX

0x203332 MOV	%RBX,%RDI

0x203335 CALL	204350 <@plt_start@+0xa0>

0x20333a ADD	$0x28,%RSP

0x20333e POP	%RBX

0x20333f POP	%R12

0x203341 POP	%R13

0x203343 POP	%R14

0x203345 POP	%R15

0x203347 POP	%RBP

0x203348 RET

0x203349 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Coverage (%)	Name	Source Location	Module
►99.38+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Coverage (%)	Name	Source Location	Module
►99.60+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x8

Source file and lines	stream.c:271-275
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271-275.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.67 to 1.50 cycles (9.78x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.67 to 0.99 cycles (14.80x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:275
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	86
nb uops	88
loop length	399
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.25	11.25	11.25	11.25	4.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	11.25	11.25	11.25	11.25	4.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.67
Dispatch	11.25
Overall L1	14.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

2% of peak load performance is reached (2.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.67 to 11.25 cycles (1.30x speedup).

ASM code

In the binary file, the address of the function is: 203170

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
LEA 0x33a5(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x10b8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204330 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x40(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV $0x3344ffff,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
CMP $0x3344ffff,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RAX,%R15	1	0.50	0	0	0.50	0	0	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
CMP %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JG 203322 <main.omp_outlined.14+0x1b2>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV $0x334501190,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R13,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA 0x8(,%R12,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R13,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CALL 204340 <@plt_start@+0x90>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
MOV $0x1190,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a281190,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
CMP $0x8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 203251 <main.omp_outlined.14+0xe1>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 2032e4 <main.omp_outlined.14+0x174>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
MOV $-0x5d58,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA (%RBX,%RAX,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVDDUP (%RBX,%R10,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50	scal (12.5%)
MOV $-0x5d78,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA 0x30(%RDX,%R13,8),%RDI	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA (%RBX,%RCX,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VMOVDDUP (%RBX,%R10,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50	scal (12.5%)
LEA 0x30(%RDX,%R13,8),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA (%R13,%RSI,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RSI,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 203322 <main.omp_outlined.14+0x1b2>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
DEC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x3ff0000000000000,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4000000000000000,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x10d0,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 204350 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x8

Source file and lines	stream.c:271-275
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.67 to 1.50 cycles (9.78x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:275
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	86
nb uops	88
loop length	399
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.25	11.25	11.25	11.25	4.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	11.25	11.25	11.25	11.25	4.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.67
Dispatch	11.25
Overall L1	14.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.67 cycles. At this rate:

2% of peak load performance is reached (2.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 203170

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
LEA 0x33a5(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x10b8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204330 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x40(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV $0x3344ffff,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
CMP $0x3344ffff,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RAX,%R15	1	0.50	0	0	0.50	0	0	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
CMP %R15,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JG 203322 <main.omp_outlined.14+0x1b2>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV $0x334501190,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R13,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA 0x8(,%R12,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R13,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CALL 204340 <@plt_start@+0x90>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
MOV $0x1190,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a281190,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
CMP $0x8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 203251 <main.omp_outlined.14+0xe1>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 2032e4 <main.omp_outlined.14+0x174>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
MOV $-0x5d58,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA (%RBX,%RAX,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVDDUP (%RBX,%R10,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50	scal (12.5%)
MOV $-0x5d78,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA 0x30(%RDX,%R13,8),%RDI	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA (%RBX,%RCX,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VMOVDDUP (%RBX,%R10,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50	scal (12.5%)
LEA 0x30(%RDX,%R13,8),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA (%R13,%RSI,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RSI,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 203322 <main.omp_outlined.14+0x1b2>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
DEC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x3ff0000000000000,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4000000000000000,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x10d0,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 204350 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

▶Scalability Runs Description

Run 1x8	Number processes: 1Number nodes: NANumber processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/run/oneview_runs/multicore/aocc_4/oneview_run_1773741893OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threadsOMP_NUM_THREADS: 8
Run 1x64	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/run/oneview_runs/multicore/aocc_4/oneview_run_1773741893OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/run/oneview_runs/multicore/aocc_4/oneview_run_1773741893OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x128	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/run/oneview_runs/multicore/aocc_4/oneview_run_1773741893OMP_NUM_THREADS: 128OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x160	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/run/oneview_runs/multicore/aocc_4/oneview_run_1773741893OMP_NUM_THREADS: 160OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x192	Number processes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/run/oneview_runs/multicore/aocc_4/oneview_run_1773741893OMP_NUM_THREADS: 192OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)	(1x128) Efficiency	(1x128) Potential Speed-Up (%)	(1x160) Efficiency	(1x160) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)
1	0	0.43	0.12	0.2	0.24	0.13	0.28	0.08	0.37	0.06	0.45

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x8	8	1	1	1	0.03999999910593	0.38317513465881
1x64	56	0.43	3.45	8	0.025000000372529	0.20443208515644
1x96	90	0.2	2.43	12	0.029999999329448	0.29831844568253
1x128	123	0.13	2.11	16	0.025000000372529	0.32676765322685
1x160	160	0.08	1.7	20	0.030000001192093	0.40253159403801
1x192	174	0.06	1.46	24	0.045000001788139	0.4843091070652

Name	Coverage (%)	Time (s)
▼main.omp_outlined.14–	0.38	0.03
○Loop 4 - stream.c:273-274 - exec	0.38	0.03
○Loop 5 - stream.c:272-274 - exec	0.00	0.00

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