OV - exec - Loop 3

	Loop Id: 3	Module: exec	Source: stream.c:344-344	Coverage: 95.48%

0x401d02 VMOVUPD	(%R8,%RCX,1),%XMM14    [1]

0x401d08 VADDPD	(%RDI,%RCX,1),%XMM14,%XMM15    [2]

0x401d0d VMOVUPD	%XMM15,(%RSI,%RCX,1)    [3]

0x401d12 VMOVUPD	0x10(%R8,%RCX,1),%XMM0    [1]

0x401d19 VADDPD	0x10(%RDI,%RCX,1),%XMM0,%XMM1    [2]

0x401d1f VMOVUPD	%XMM1,0x10(%RSI,%RCX,1)    [3]

0x401d25 VMOVUPD	0x20(%R8,%RCX,1),%XMM2    [1]

0x401d2c VADDPD	0x20(%RDI,%RCX,1),%XMM2,%XMM3    [2]

0x401d32 VMOVUPD	%XMM3,0x20(%RSI,%RCX,1)    [3]

0x401d38 VMOVUPD	0x30(%R8,%RCX,1),%XMM4    [1]

0x401d3f VADDPD	0x30(%RDI,%RCX,1),%XMM4,%XMM5    [2]

0x401d45 VMOVUPD	%XMM5,0x30(%RSI,%RCX,1)    [3]

0x401d4b VMOVUPD	0x40(%R8,%RCX,1),%XMM6    [1]

0x401d52 VADDPD	0x40(%RDI,%RCX,1),%XMM6,%XMM7    [2]

0x401d58 VMOVUPD	%XMM7,0x40(%RSI,%RCX,1)    [3]

0x401d5e VMOVUPD	0x50(%R8,%RCX,1),%XMM8    [1]

0x401d65 VADDPD	0x50(%RDI,%RCX,1),%XMM8,%XMM9    [2]

0x401d6b VMOVUPD	%XMM9,0x50(%RSI,%RCX,1)    [3]

0x401d71 VMOVUPD	0x60(%R8,%RCX,1),%XMM10    [1]

0x401d78 VADDPD	0x60(%RDI,%RCX,1),%XMM10,%XMM11    [2]

0x401d7e VMOVUPD	%XMM11,0x60(%RSI,%RCX,1)    [3]

0x401d84 VMOVUPD	0x70(%R8,%RCX,1),%XMM12    [1]

0x401d8b VADDPD	0x70(%RDI,%RCX,1),%XMM12,%XMM13    [2]

0x401d91 VMOVUPD	%XMM13,0x70(%RSI,%RCX,1)    [3]

0x401d97 SUB	$-0x80,%RCX

0x401d9b CMP	%RCX,%R10

0x401d9e JNE	401d02

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 344 - 344

--------------------------------------------------------------------------------

344: 	    c[j] = a[j]+b[j];

Coverage (%)	Name	Source Location	Module
○98.95	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.05	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.85
Bottlenecks	P5, P6, P7,
Function	main._omp_fn.4
Source	stream.c:344-344
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	3.33
Front-end cycles	4.33
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	16.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.85
Bottlenecks	P5, P6, P7,
Function	main._omp_fn.4
Source	stream.c:344-344
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	3.33
Front-end cycles	4.33
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	16.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.4
Source file and lines	stream.c:344-344
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 3.33 cycles (2.40x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 8.00 to 4.33 cycles (1.85x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

16: addition or subtraction

The binary loop is loading 256 bytes (32 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	27
nb uops	26
loop length	162
used x86 registers	5
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	0.00	0.00	4.00	4.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	0.00	0.00	4.00	4.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.33
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (16.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401d02

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVUPD (%R8,%RCX,1),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD (%RDI,%RCX,1),%XMM14,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM15,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x10(%R8,%RCX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x10(%RDI,%RCX,1),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM1,0x10(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x20(%R8,%RCX,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x20(%RDI,%RCX,1),%XMM2,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM3,0x20(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x30(%R8,%RCX,1),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x30(%RDI,%RCX,1),%XMM4,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM5,0x30(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x40(%R8,%RCX,1),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x40(%RDI,%RCX,1),%XMM6,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM7,0x40(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x50(%R8,%RCX,1),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x50(%RDI,%RCX,1),%XMM8,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM9,0x50(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x60(%R8,%RCX,1),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x60(%RDI,%RCX,1),%XMM10,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM11,0x60(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x70(%R8,%RCX,1),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x70(%RDI,%RCX,1),%XMM12,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM13,0x70(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
SUB $-0x80,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RCX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 401d02 <main._omp_fn.4+0x182>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	main._omp_fn.4
Source file and lines	stream.c:344-344
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 3.33 cycles (2.40x speedup).

Details

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 8.00 to 4.33 cycles (1.85x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

16: addition or subtraction

The binary loop is loading 256 bytes (32 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	27
nb uops	26
loop length	162
used x86 registers	5
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	0.00	0.00	4.00	4.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	0.00	0.00	4.00	4.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.33
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (16.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401d02

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVUPD (%R8,%RCX,1),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD (%RDI,%RCX,1),%XMM14,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM15,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x10(%R8,%RCX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x10(%RDI,%RCX,1),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM1,0x10(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x20(%R8,%RCX,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x20(%RDI,%RCX,1),%XMM2,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM3,0x20(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x30(%R8,%RCX,1),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x30(%RDI,%RCX,1),%XMM4,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM5,0x30(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x40(%R8,%RCX,1),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x40(%RDI,%RCX,1),%XMM6,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM7,0x40(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x50(%R8,%RCX,1),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x50(%RDI,%RCX,1),%XMM8,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM9,0x50(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x60(%R8,%RCX,1),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x60(%RDI,%RCX,1),%XMM10,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM11,0x60(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD 0x70(%R8,%RCX,1),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD 0x70(%RDI,%RCX,1),%XMM12,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM13,0x70(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
SUB $-0x80,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RCX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 401d02 <main._omp_fn.4+0x182>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code