OV - exec - Function main._omp

	Function: main._omp_fn.2	Module: exec	Source: stream.c:271-275	Coverage (incl. loops): 0.97% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 271 - 275

--------------------------------------------------------------------------------

271: #pragma omp parallel for

272:     for (j=0; j<STREAM_ARRAY_SIZE; j++) {

273: 	    a[j] = 1.0;

274: 	    b[j] = 2.0;

275: 	    c[j] = 0.0;

0x401ff0 PUSH	%RBP

0x401ff1 MOV	$0x401060,%RAX

0x401ffb MOV	%RSP,%RBP

0x401ffe PUSH	%R12

0x402000 PUSH	%RBX

0x402001 CALL	%RAX

0x402003 MOVSXD	%EAX,%RBX

0x402006 MOV	$0x401030,%R12

0x402010 CALL	%R12

0x402013 MOVSXD	%EAX,%RCX

0x402016 MOV	$0x33450000,%EAX

0x40201b CQTO

0x40201d IDIV	%RBX

0x402020 CMP	%RDX,%RCX

0x402023 JL	402290

0x402029 IMUL	%RAX,%RCX

0x40202d ADD	%RCX,%RDX

0x402030 LEA	(%RAX,%RDX,1),%RSI

0x402034 CMP	%RSI,%RDX

0x402037 JGE	402281

0x40203d MOV	$0x3349060e0,%R11

0x402047 MOV	$0x19a6860e0,%RBX

0x402051 MOV	$0x4060e0,%R12

0x40205b CMP	$0x1,%RAX

0x40205f JE	402244

0x402065 MOV	%RAX,%R10

0x402068 MOV	$0x4046e0,%R9

0x402072 LEA	(,%RDX,8),%RSI

0x40207a MOV	$0x3349060e0,%R11

0x402084 SHR	$0x1,%R10

0x402087 VXORPD	%XMM0,%XMM0,%XMM0

0x40208b SAL	$0x4,%R10

0x40208f VMOVAPD	(%R9),%XMM2

0x402094 MOV	$0x4046f0,%R9

0x40209e MOV	$0x19a6860e0,%RBX

0x4020a8 MOV	$0x4060e0,%R12

0x4020b2 VMOVAPD	(%R9),%XMM1

0x4020b7 LEA	-0x10(%R10),%R9

0x4020bb LEA	(%R11,%RSI,1),%R8

0x4020bf LEA	(%RBX,%RSI,1),%RDI

0x4020c3 SHR	$0x4,%R9

0x4020c7 INC	%R9

0x4020ca ADD	%R12,%RSI

0x4020cd XOR	%ECX,%ECX

0x4020cf AND	$0x7,%R9D

0x4020d3 JE	402194

0x4020d9 CMP	$0x1,%R9

0x4020dd JE	402177

0x4020e3 CMP	$0x2,%R9

0x4020e7 JE	402163

0x4020e9 CMP	$0x3,%R9

0x4020ed JE	40214f

0x4020ef CMP	$0x4,%R9

0x4020f3 JE	40213b

0x4020f5 CMP	$0x5,%R9

0x4020f9 JE	402127

0x4020fb CMP	$0x6,%R9

0x4020ff JE	402113

0x402101 VMOVUPD	%XMM2,(%R8)

0x402106 MOV	$0x10,%ECX

0x40210b VMOVUPD	%XMM1,(%RDI)

0x40210f VMOVUPD	%XMM0,(%RSI)

0x402113 VMOVUPD	%XMM2,(%R8,%RCX,1)

0x402119 VMOVUPD	%XMM1,(%RDI,%RCX,1)

0x40211e VMOVUPD	%XMM0,(%RSI,%RCX,1)

0x402123 ADD	$0x10,%RCX

0x402127 VMOVUPD	%XMM2,(%R8,%RCX,1)

0x40212d VMOVUPD	%XMM1,(%RDI,%RCX,1)

0x402132 VMOVUPD	%XMM0,(%RSI,%RCX,1)

0x402137 ADD	$0x10,%RCX

0x40213b VMOVUPD	%XMM2,(%R8,%RCX,1)

0x402141 VMOVUPD	%XMM1,(%RDI,%RCX,1)

0x402146 VMOVUPD	%XMM0,(%RSI,%RCX,1)

0x40214b ADD	$0x10,%RCX

0x40214f VMOVUPD	%XMM2,(%R8,%RCX,1)

0x402155 VMOVUPD	%XMM1,(%RDI,%RCX,1)

0x40215a VMOVUPD	%XMM0,(%RSI,%RCX,1)

0x40215f ADD	$0x10,%RCX

0x402163 VMOVUPD	%XMM2,(%R8,%RCX,1)

0x402169 VMOVUPD	%XMM1,(%RDI,%RCX,1)

0x40216e VMOVUPD	%XMM0,(%RSI,%RCX,1)

0x402173 ADD	$0x10,%RCX

0x402177 VMOVUPD	%XMM2,(%R8,%RCX,1)

0x40217d VMOVUPD	%XMM1,(%RDI,%RCX,1)

0x402182 VMOVUPD	%XMM0,(%RSI,%RCX,1)

0x402187 ADD	$0x10,%RCX

0x40218b CMP	%RCX,%R10

0x40218e JE	402236

(5) 0x402194 VMOVUPD	%XMM2,(%R8,%RCX,1)

(5) 0x40219a VMOVUPD	%XMM1,(%RDI,%RCX,1)

(5) 0x40219f VMOVUPD	%XMM0,(%RSI,%RCX,1)

(5) 0x4021a4 VMOVUPD	%XMM2,0x10(%R8,%RCX,1)

(5) 0x4021ab VMOVUPD	%XMM1,0x10(%RDI,%RCX,1)

(5) 0x4021b1 VMOVUPD	%XMM0,0x10(%RSI,%RCX,1)

(5) 0x4021b7 VMOVUPD	%XMM2,0x20(%R8,%RCX,1)

(5) 0x4021be VMOVUPD	%XMM1,0x20(%RDI,%RCX,1)

(5) 0x4021c4 VMOVUPD	%XMM0,0x20(%RSI,%RCX,1)

(5) 0x4021ca VMOVUPD	%XMM2,0x30(%R8,%RCX,1)

(5) 0x4021d1 VMOVUPD	%XMM1,0x30(%RDI,%RCX,1)

(5) 0x4021d7 VMOVUPD	%XMM0,0x30(%RSI,%RCX,1)

(5) 0x4021dd VMOVUPD	%XMM2,0x40(%R8,%RCX,1)

(5) 0x4021e4 VMOVUPD	%XMM1,0x40(%RDI,%RCX,1)

(5) 0x4021ea VMOVUPD	%XMM0,0x40(%RSI,%RCX,1)

(5) 0x4021f0 VMOVUPD	%XMM2,0x50(%R8,%RCX,1)

(5) 0x4021f7 VMOVUPD	%XMM1,0x50(%RDI,%RCX,1)

(5) 0x4021fd VMOVUPD	%XMM0,0x50(%RSI,%RCX,1)

(5) 0x402203 VMOVUPD	%XMM2,0x60(%R8,%RCX,1)

(5) 0x40220a VMOVUPD	%XMM1,0x60(%RDI,%RCX,1)

(5) 0x402210 VMOVUPD	%XMM0,0x60(%RSI,%RCX,1)

(5) 0x402216 VMOVUPD	%XMM2,0x70(%R8,%RCX,1)

(5) 0x40221d VMOVUPD	%XMM1,0x70(%RDI,%RCX,1)

(5) 0x402223 VMOVUPD	%XMM0,0x70(%RSI,%RCX,1)

(5) 0x402229 SUB	$-0x80,%RCX

(5) 0x40222d CMP	%RCX,%R10

(5) 0x402230 JNE	402194

0x402236 MOV	%RAX,%RSI

0x402239 AND	$-0x2,%RSI

0x40223d TEST	$0x1,%AL

0x40223f JE	402281

0x402241 ADD	%RSI,%RDX

0x402244 MOV	$0x4046e0,%RAX

0x40224e MOV	$0x404738,%R8

0x402258 VMOVSD	(%RAX),%XMM3

0x40225c VMOVSD	%XMM3,(%R11,%RDX,8)

0x402262 MOV	$0x4046f0,%R11

0x40226c VMOVSD	(%R8),%XMM5

0x402271 VMOVSD	(%R11),%XMM4

0x402276 VMOVSD	%XMM5,(%R12,%RDX,8)

0x40227c VMOVSD	%XMM4,(%RBX,%RDX,8)

0x402281 POP	%RBX

0x402282 POP	%R12

0x402284 POP	%RBP

0x402285 RET

0x402286 NOPW	%CS:(%RAX,%RAX,1)

0x402290 INC	%RAX

0x402293 XOR	%EDX,%EDX

0x402295 JMP	402029

0x40229a NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○98.92	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.08	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	stream.c:271-275
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271-275.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.50 to 12.00 cycles (1.54x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 19% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 18.50 to 3.00 cycles (6.17x speedup).

Details

55% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
87% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
7% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 360 bytes.

General properties

nb instructions	111
nb uops	111
loop length	526
used x86 registers	13
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.50 cycles
front end	18.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	14.75	14.75	14.75	14.75	9.00	10.33	10.33	10.33	0.00	0.00	0.00	0.00	12.00	12.00
cycles	14.75	14.75	14.75	14.75	9.00	10.33	10.33	10.33	0.00	0.00	0.00	0.00	12.00	12.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	18.50
Dispatch	14.75
DIV/SQRT	7.00-12.00
Overall L1	18.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	80%
load	40%
store	87%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	55%
load	40%
store	87%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	22%
load	17%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	19%
load	17%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.50 cycles. At this rate:

3% of peak load performance is reached (3.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (19.46 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.50 to 14.75 cycles (1.25x speedup).

ASM code

In the binary file, the address of the function is: 401ff0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x401030,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CALL %R12	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 402290 <main._omp_fn.2+0x2a0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 402281 <main._omp_fn.2+0x291>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x3349060e0,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a6860e0,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x4060e0,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402244 <main._omp_fn.2+0x254>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4046e0,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x3349060e0,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x1,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SAL $0x4,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVAPD (%R9),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV $0x4046f0,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a6860e0,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x4060e0,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVAPD (%R9),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
LEA -0x10(%R10),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RSI,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x4,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x7,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402194 <main._omp_fn.2+0x1a4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402177 <main._omp_fn.2+0x187>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402163 <main._omp_fn.2+0x173>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40214f <main._omp_fn.2+0x15f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40213b <main._omp_fn.2+0x14b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402127 <main._omp_fn.2+0x137>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402113 <main._omp_fn.2+0x123>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD %XMM2,(%R8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
MOV $0x10,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM1,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RCX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402236 <main._omp_fn.2+0x246>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TEST $0x1,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402281 <main._omp_fn.2+0x291>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4046e0,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x404738,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RAX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,(%R11,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x4046f0,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%R8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM5,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM4,(%RBX,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 402029 <main._omp_fn.2+0x39>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	stream.c:271-275
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

55% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
87% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
7% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:271

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 360 bytes.

General properties

nb instructions	111
nb uops	111
loop length	526
used x86 registers	13
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.50 cycles
front end	18.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	14.75	14.75	14.75	14.75	9.00	10.33	10.33	10.33	0.00	0.00	0.00	0.00	12.00	12.00
cycles	14.75	14.75	14.75	14.75	9.00	10.33	10.33	10.33	0.00	0.00	0.00	0.00	12.00	12.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	18.50
Dispatch	14.75
DIV/SQRT	7.00-12.00
Overall L1	18.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	80%
load	40%
store	87%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	55%
load	40%
store	87%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	22%
load	17%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	19%
load	17%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.50 cycles. At this rate:

3% of peak load performance is reached (3.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (19.46 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401ff0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x401030,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CALL %R12	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 402290 <main._omp_fn.2+0x2a0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 402281 <main._omp_fn.2+0x291>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x3349060e0,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a6860e0,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x4060e0,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402244 <main._omp_fn.2+0x254>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4046e0,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x3349060e0,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x1,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SAL $0x4,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVAPD (%R9),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV $0x4046f0,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a6860e0,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x4060e0,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVAPD (%R9),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
LEA -0x10(%R10),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%RSI,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x4,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x7,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402194 <main._omp_fn.2+0x1a4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402177 <main._omp_fn.2+0x187>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402163 <main._omp_fn.2+0x173>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40214f <main._omp_fn.2+0x15f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40213b <main._omp_fn.2+0x14b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402127 <main._omp_fn.2+0x137>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402113 <main._omp_fn.2+0x123>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD %XMM2,(%R8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
MOV $0x10,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM1,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %XMM2,(%R8,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,(%RDI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM0,(%RSI,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RCX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402236 <main._omp_fn.2+0x246>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TEST $0x1,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402281 <main._omp_fn.2+0x291>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4046e0,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x404738,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RAX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,(%R11,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x4046f0,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%R8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R11),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM5,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD %XMM4,(%RBX,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 402029 <main._omp_fn.2+0x39>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.2–	0.97	0.07
○Loop 5 - stream.c:273-275 - exec	0.97	0.07

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code