OV - exec - Function main._omp

	Function: main._omp_fn.3	Module: exec	Source: stream.c:290-292	Coverage (incl. loops): 0.48% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 290 - 292

--------------------------------------------------------------------------------

290: #pragma omp parallel for

291:     for (j = 0; j < STREAM_ARRAY_SIZE; j++)

292: 		a[j] = 2.0E0 * a[j];

0x401de0 PUSH	%RBP

0x401de1 MOV	$0x401060,%RAX

0x401deb MOV	%RSP,%RBP

0x401dee PUSH	%RBX

0x401def SUB	$0x8,%RSP

0x401df3 CALL	%RAX

0x401df5 MOVSXD	%EAX,%RBX

0x401df8 MOV	$0x401030,%RAX

0x401e02 CALL	%RAX

0x401e04 MOVSXD	%EAX,%RCX

0x401e07 MOV	$0x33450000,%EAX

0x401e0c CQTO

0x401e0e IDIV	%RBX

0x401e11 CMP	%RDX,%RCX

0x401e14 JL	401fe0

0x401e1a IMUL	%RAX,%RCX

0x401e1e ADD	%RCX,%RDX

0x401e21 LEA	(%RAX,%RDX,1),%RSI

0x401e25 CMP	%RSI,%RDX

0x401e28 JGE	401fcf

0x401e2e MOV	$0x3349060e0,%RDI

0x401e38 CMP	$0x1,%RAX

0x401e3c JE	401fc0

0x401e42 MOV	%RAX,%R10

0x401e45 LEA	(%RDI,%RDX,8),%R9

0x401e49 SHR	$0x1,%R10

0x401e4c SAL	$0x4,%R10

0x401e50 LEA	(%R10,%R9,1),%R8

0x401e54 SUB	$0x10,%R10

0x401e58 SHR	$0x4,%R10

0x401e5c INC	%R10

0x401e5f AND	$0x7,%R10D

0x401e63 JE	401f22

0x401e69 CMP	$0x1,%R10

0x401e6d JE	401f05

0x401e73 CMP	$0x2,%R10

0x401e77 JE	401ef1

0x401e79 CMP	$0x3,%R10

0x401e7d JE	401edd

0x401e7f CMP	$0x4,%R10

0x401e83 JE	401eca

0x401e85 CMP	$0x5,%R10

0x401e89 JE	401eb7

0x401e8b CMP	$0x6,%R10

0x401e8f JE	401ea4

0x401e91 VMOVUPD	(%R9),%XMM0

0x401e96 ADD	$0x10,%R9

0x401e9a VADDPD	%XMM0,%XMM0,%XMM1

0x401e9e VMOVUPD	%XMM1,-0x10(%R9)

0x401ea4 VMOVUPD	(%R9),%XMM2

0x401ea9 ADD	$0x10,%R9

0x401ead VADDPD	%XMM2,%XMM2,%XMM3

0x401eb1 VMOVUPD	%XMM3,-0x10(%R9)

0x401eb7 VMOVUPD	(%R9),%XMM4

0x401ebc ADD	$0x10,%R9

0x401ec0 VADDPD	%XMM4,%XMM4,%XMM5

0x401ec4 VMOVUPD	%XMM5,-0x10(%R9)

0x401eca VMOVUPD	(%R9),%XMM6

0x401ecf ADD	$0x10,%R9

0x401ed3 VADDPD	%XMM6,%XMM6,%XMM7

0x401ed7 VMOVUPD	%XMM7,-0x10(%R9)

0x401edd VMOVUPD	(%R9),%XMM8

0x401ee2 ADD	$0x10,%R9

0x401ee6 VADDPD	%XMM8,%XMM8,%XMM9

0x401eeb VMOVUPD	%XMM9,-0x10(%R9)

0x401ef1 VMOVUPD	(%R9),%XMM10

0x401ef6 ADD	$0x10,%R9

0x401efa VADDPD	%XMM10,%XMM10,%XMM11

0x401eff VMOVUPD	%XMM11,-0x10(%R9)

0x401f05 VMOVUPD	(%R9),%XMM12

0x401f0a ADD	$0x10,%R9

0x401f0e VADDPD	%XMM12,%XMM12,%XMM13

0x401f13 VMOVUPD	%XMM13,-0x10(%R9)

0x401f19 CMP	%R8,%R9

0x401f1c JE	401fb2

(4) 0x401f22 VMOVUPD	(%R9),%XMM14

(4) 0x401f27 VMOVUPD	0x10(%R9),%XMM0

(4) 0x401f2d VMOVUPD	0x20(%R9),%XMM2

(4) 0x401f33 SUB	$-0x80,%R9

(4) 0x401f37 VMOVUPD	-0x50(%R9),%XMM4

(4) 0x401f3d VMOVUPD	-0x40(%R9),%XMM6

(4) 0x401f43 VMOVUPD	-0x30(%R9),%XMM8

(4) 0x401f49 VMOVUPD	-0x20(%R9),%XMM10

(4) 0x401f4f VMOVUPD	-0x10(%R9),%XMM12

(4) 0x401f55 VADDPD	%XMM14,%XMM14,%XMM15

(4) 0x401f5a VADDPD	%XMM0,%XMM0,%XMM1

(4) 0x401f5e VADDPD	%XMM2,%XMM2,%XMM3

(4) 0x401f62 VADDPD	%XMM4,%XMM4,%XMM5

(4) 0x401f66 VADDPD	%XMM6,%XMM6,%XMM7

(4) 0x401f6a VADDPD	%XMM8,%XMM8,%XMM9

(4) 0x401f6f VADDPD	%XMM10,%XMM10,%XMM11

(4) 0x401f74 VADDPD	%XMM12,%XMM12,%XMM13

(4) 0x401f79 VMOVUPD	%XMM15,-0x80(%R9)

(4) 0x401f7f VMOVUPD	%XMM1,-0x70(%R9)

(4) 0x401f85 VMOVUPD	%XMM3,-0x60(%R9)

(4) 0x401f8b VMOVUPD	%XMM5,-0x50(%R9)

(4) 0x401f91 VMOVUPD	%XMM7,-0x40(%R9)

(4) 0x401f97 VMOVUPD	%XMM9,-0x30(%R9)

(4) 0x401f9d VMOVUPD	%XMM11,-0x20(%R9)

(4) 0x401fa3 VMOVUPD	%XMM13,-0x10(%R9)

(4) 0x401fa9 CMP	%R8,%R9

(4) 0x401fac JNE	401f22

0x401fb2 MOV	%RAX,%R11

0x401fb5 AND	$-0x2,%R11

0x401fb9 TEST	$0x1,%AL

0x401fbb JE	401fcf

0x401fbd ADD	%R11,%RDX

0x401fc0 VMOVSD	(%RDI,%RDX,8),%XMM14

0x401fc5 VADDSD	%XMM14,%XMM14,%XMM15

0x401fca VMOVSD	%XMM15,(%RDI,%RDX,8)

0x401fcf MOV	-0x8(%RBP),%RBX

0x401fd3 LEAVE

0x401fd4 RET

0x401fd5 NOPW	%CS:(%RAX,%RAX,1)

0x401fe0 INC	%RAX

0x401fe3 XOR	%EDX,%EDX

0x401fe5 JMP	401e1a

0x401fea NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○98.82	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.18	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	stream.c:290-292
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290-292.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.33 to 6.83 cycles (2.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 15.33 to 3.00 cycles (5.11x speedup).

Details

48% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

77% of SSE/AVX loads are used in vector version.
87% of SSE/AVX stores are used in vector version.
77% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290
LEAVE: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 15 FP arithmetical operations:

15: addition or subtraction

The binary function is loading 128 bytes (16 double precision FP elements). The binary function is storing 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	91
nb uops	92
loop length	384
used x86 registers	12
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.25	12.25	12.25	12.25	9.00	6.67	6.67	6.67	0.00	0.00	4.00	4.00	4.00	4.00
cycles	12.25	12.25	12.25	12.25	9.00	6.67	6.67	6.67	0.00	0.00	4.00	4.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	15.33
Dispatch	12.25
DIV/SQRT	7.00-12.00
Overall L1	15.33

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	87%
load	87%
store	87%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	87%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	48%
load	77%
store	87%
mul	0%
add-sub	77%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	23%
load	23%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	18%
load	22%
store	23%
mul	12%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.33 cycles. At this rate:

8% of peak load performance is reached (8.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (7.83 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.33 to 12.25 cycles (1.25x speedup).

ASM code

In the binary file, the address of the function is: 401de0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 401fe0 <main._omp_fn.3+0x200>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 401fcf <main._omp_fn.3+0x1ef>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x3349060e0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401fc0 <main._omp_fn.3+0x1e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%RDX,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x1,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SAL $0x4,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA (%R10,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB $0x10,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x4,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND $0x7,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 401f22 <main._omp_fn.3+0x142>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401f05 <main._omp_fn.3+0x125>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401ef1 <main._omp_fn.3+0x111>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401edd <main._omp_fn.3+0xfd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401eca <main._omp_fn.3+0xea>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401eb7 <main._omp_fn.3+0xd7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401ea4 <main._omp_fn.3+0xc4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R9),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM1,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM3,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM4,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM5,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM6,%XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM7,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM9,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM10,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM11,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM12,%XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM13,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
CMP %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401fb2 <main._omp_fn.3+0x1d2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x2,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
TEST $0x1,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 401fcf <main._omp_fn.3+0x1ef>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RDI,%RDX,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM14,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM15,(%RDI,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
MOV -0x8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (12.5%)
LEAVE	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 401e1a <main._omp_fn.3+0x3a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	stream.c:290-292
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.33 to 6.83 cycles (2.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

48% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

77% of SSE/AVX loads are used in vector version.
87% of SSE/AVX stores are used in vector version.
77% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290
LEAVE: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 15 FP arithmetical operations:

15: addition or subtraction

The binary function is loading 128 bytes (16 double precision FP elements). The binary function is storing 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	91
nb uops	92
loop length	384
used x86 registers	12
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.33 cycles
front end	15.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.25	12.25	12.25	12.25	9.00	6.67	6.67	6.67	0.00	0.00	4.00	4.00	4.00	4.00
cycles	12.25	12.25	12.25	12.25	9.00	6.67	6.67	6.67	0.00	0.00	4.00	4.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	15.33
Dispatch	12.25
DIV/SQRT	7.00-12.00
Overall L1	15.33

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	87%
load	87%
store	87%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	87%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	48%
load	77%
store	87%
mul	0%
add-sub	77%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	23%
load	23%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	18%
load	22%
store	23%
mul	12%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.33 cycles. At this rate:

8% of peak load performance is reached (8.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (7.83 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 401de0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 401fe0 <main._omp_fn.3+0x200>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 401fcf <main._omp_fn.3+0x1ef>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x3349060e0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401fc0 <main._omp_fn.3+0x1e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%RDX,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x1,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SAL $0x4,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA (%R10,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB $0x10,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x4,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND $0x7,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 401f22 <main._omp_fn.3+0x142>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401f05 <main._omp_fn.3+0x125>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401ef1 <main._omp_fn.3+0x111>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401edd <main._omp_fn.3+0xfd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401eca <main._omp_fn.3+0xea>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401eb7 <main._omp_fn.3+0xd7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401ea4 <main._omp_fn.3+0xc4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R9),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM1,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM3,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM4,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM5,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM6,%XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM7,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM9,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM10,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM11,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD (%R9),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VADDPD %XMM12,%XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM13,-0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (25.0%)
CMP %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 401fb2 <main._omp_fn.3+0x1d2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x2,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
TEST $0x1,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 401fcf <main._omp_fn.3+0x1ef>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RDI,%RDX,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM14,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM15,(%RDI,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
MOV -0x8(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (12.5%)
LEAVE	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 401e1a <main._omp_fn.3+0x3a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.3–	0.48	0.04
○Loop 4 - stream.c:292-292 - exec	0.48	0.04

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