OV - exec - Function main.extracted.50

	Function: main.extracted.50	Module: exec	Source: stream.c:342-344	Coverage (incl. loops): 94.71% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 342 - 344

--------------------------------------------------------------------------------

342: #pragma omp parallel for

343: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

344: 	    c[j] = a[j]+b[j];

0x4030f0 PUSH	%RBP

0x4030f1 MOV	%RSP,%RBP

0x4030f4 PUSH	%R15

0x4030f6 PUSH	%R14

0x4030f8 PUSH	%RBX

0x4030f9 SUB	$0x28,%RSP

0x4030fd MOVL	$0,-0x1c(%RBP)

0x403104 MOV	(%RDI),%EBX

0x403106 MOVQ	$0,-0x30(%RBP)

0x40310e MOVQ	$0x3344ffff,-0x28(%RBP)

0x403116 MOVQ	$0x1,-0x38(%RBP)

0x40311e SUB	$0x8,%RSP

0x403122 LEA	-0x38(%RBP),%RAX

0x403126 MOV	$0x4ceb88e10,%RDI

0x403130 MOV	$0x401050,%R10

0x40313a LEA	-0x1c(%RBP),%RCX

0x40313e LEA	-0x30(%RBP),%R8

0x403142 LEA	-0x28(%RBP),%R9

0x403146 MOV	%EBX,%ESI

0x403148 MOV	$0x22,%EDX

0x40314d PUSH	$0x1

0x40314f PUSH	$0x1

0x403151 PUSH	%RAX

0x403152 CALL	%R10

0x403155 ADD	$0x20,%RSP

0x403159 MOV	-0x30(%RBP),%RAX

0x40315d MOV	-0x28(%RBP),%RDI

0x403161 CMP	%RDI,%RAX

0x403164 JA	4033a1

0x40316a MOV	%RDI,%R8

0x40316d SUB	%RAX,%R8

0x403170 MOV	$0x19a686060,%RCX

0x40317a MOV	$0x406060,%RDX

0x403184 MOV	$0x334906060,%RSI

0x40318e INC	%R8

0x403191 CMP	$0x8,%R8

0x403195 JB	403259

0x40319b LEA	0x38(,%RAX,8),%R10

0x4031a3 MOV	%R8,%R9

0x4031a6 SHR	$0x3,%R9

0x4031aa NOPW	(%RAX,%RAX,1)

(13) 0x4031b0 LEA	-0x38(%R10,%RCX,1),%R11

(13) 0x4031b5 LEA	-0x38(%R10,%RDX,1),%R14

(13) 0x4031ba LEA	-0x38(%R10,%RSI,1),%R15

(13) 0x4031bf ADD	$0x40,%R10

(13) 0x4031c3 DEC	%R9

(13) 0x4031c6 VMOVSD	(%R11),%XMM0

(13) 0x4031cb VADDSD	(%R14),%XMM0,%XMM0

(13) 0x4031d0 VMOVSD	%XMM0,(%R15)

(13) 0x4031d5 VMOVSD	0x8(%R11),%XMM0

(13) 0x4031db VADDSD	0x8(%R14),%XMM0,%XMM0

(13) 0x4031e1 VMOVSD	%XMM0,0x8(%R15)

(13) 0x4031e7 VMOVSD	0x10(%R11),%XMM0

(13) 0x4031ed VADDSD	0x10(%R14),%XMM0,%XMM0

(13) 0x4031f3 VMOVSD	%XMM0,0x10(%R15)

(13) 0x4031f9 VMOVSD	0x18(%R11),%XMM0

(13) 0x4031ff VADDSD	0x18(%R14),%XMM0,%XMM0

(13) 0x403205 VMOVSD	%XMM0,0x18(%R15)

(13) 0x40320b VMOVSD	0x20(%R11),%XMM0

(13) 0x403211 VADDSD	0x20(%R14),%XMM0,%XMM0

(13) 0x403217 VMOVSD	%XMM0,0x20(%R15)

(13) 0x40321d VMOVSD	0x28(%R11),%XMM0

(13) 0x403223 VADDSD	0x28(%R14),%XMM0,%XMM0

(13) 0x403229 VMOVSD	%XMM0,0x28(%R15)

(13) 0x40322f VMOVSD	0x30(%R11),%XMM0

(13) 0x403235 VADDSD	0x30(%R14),%XMM0,%XMM0

(13) 0x40323b VMOVSD	%XMM0,0x30(%R15)

(13) 0x403241 VMOVSD	0x38(%R11),%XMM0

(13) 0x403247 VADDSD	0x38(%R14),%XMM0,%XMM0

(13) 0x40324d VMOVSD	%XMM0,0x38(%R15)

(13) 0x403253 JNE	4031b0

0x403259 AND	$0x7ffffff8,%R8D

0x403260 ADD	%R8,%RAX

0x403263 SUB	%RAX,%RDI

0x403266 CMP	$0x6,%RDI

0x40326a JA	4033a1

0x403270 MOV	$0x404140,%R8

0x40327a JMP	(%R8,%RDI,8)

0x40327e MOV	$0x19a686090,%RDI

0x403288 MOV	$0x406090,%R8

0x403292 VMOVSD	(%RDI,%RAX,8),%XMM0

0x403297 MOV	$0x334906090,%RDI

0x4032a1 VADDSD	(%R8,%RAX,8),%XMM0,%XMM0

0x4032a7 VMOVSD	%XMM0,(%RDI,%RAX,8)

0x4032ac MOV	$0x19a686088,%RDI

0x4032b6 MOV	$0x406088,%R8

0x4032c0 VMOVSD	(%RDI,%RAX,8),%XMM0

0x4032c5 MOV	$0x334906088,%RDI

0x4032cf VADDSD	(%R8,%RAX,8),%XMM0,%XMM0

0x4032d5 VMOVSD	%XMM0,(%RDI,%RAX,8)

0x4032da MOV	$0x19a686080,%RDI

0x4032e4 MOV	$0x406080,%R8

0x4032ee VMOVSD	(%RDI,%RAX,8),%XMM0

0x4032f3 MOV	$0x334906080,%RDI

0x4032fd VADDSD	(%R8,%RAX,8),%XMM0,%XMM0

0x403303 VMOVSD	%XMM0,(%RDI,%RAX,8)

0x403308 MOV	$0x19a686078,%RDI

0x403312 MOV	$0x406078,%R8

0x40331c VMOVSD	(%RDI,%RAX,8),%XMM0

0x403321 MOV	$0x334906078,%RDI

0x40332b VADDSD	(%R8,%RAX,8),%XMM0,%XMM0

0x403331 VMOVSD	%XMM0,(%RDI,%RAX,8)

0x403336 MOV	$0x19a686070,%RDI

0x403340 MOV	$0x406070,%R8

0x40334a VMOVSD	(%RDI,%RAX,8),%XMM0

0x40334f MOV	$0x334906070,%RDI

0x403359 VADDSD	(%R8,%RAX,8),%XMM0,%XMM0

0x40335f VMOVSD	%XMM0,(%RDI,%RAX,8)

0x403364 MOV	$0x19a686068,%RDI

0x40336e MOV	$0x406068,%R8

0x403378 VMOVSD	(%RDI,%RAX,8),%XMM0

0x40337d MOV	$0x334906068,%RDI

0x403387 VADDSD	(%R8,%RAX,8),%XMM0,%XMM0

0x40338d VMOVSD	%XMM0,(%RDI,%RAX,8)

0x403392 VMOVSD	(%RCX,%RAX,8),%XMM0

0x403397 VADDSD	(%RDX,%RAX,8),%XMM0,%XMM0

0x40339c VMOVSD	%XMM0,(%RSI,%RAX,8)

0x4033a1 MOV	$0x4ceb88e30,%RDI

0x4033ab MOV	$0x401030,%RAX

0x4033b5 MOV	%EBX,%ESI

0x4033b7 ADD	$0x28,%RSP

0x4033bb POP	%RBX

0x4033bc POP	%R14

0x4033be POP	%R15

0x4033c0 POP	%RBP

0x4033c1 JMP	%RAX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	stream.c:342-344
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342-344.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.17 to 7.00 cycles (2.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.17 to 1.79 cycles (9.02x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

7: addition or subtraction

The binary function is loading 140 bytes (17 double precision FP elements). The binary function is storing 84 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	97
loop length	554
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.17 cycles
front end	16.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.00	12.00	12.00	12.00	3.00	10.00	10.00	10.00	0.00	0.00	3.50	3.50	3.50	3.50
cycles	12.00	12.00	12.00	12.00	3.00	10.00	10.00	10.00	0.00	0.00	3.50	3.50	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.17
Dispatch	12.00
Overall L1	16.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.17 cycles. At this rate:

9% of peak load performance is reached (8.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.20 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.17 to 12.00 cycles (1.35x speedup).

ASM code

In the binary file, the address of the function is: 4030f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88e10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x1c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
MOV -0x28(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4033a1 <main.extracted.50+0x2b1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x19a686060,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334906060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x8,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 403259 <main.extracted.50+0x169>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x38(,%RAX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x3,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $0x7ffffff8,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x6,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4033a1 <main.extracted.50+0x2b1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x404140,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP (%R8,%RDI,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV $0x19a686090,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406090,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906090,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x19a686088,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406088,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906088,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x19a686080,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406080,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906080,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x19a686078,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406078,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906078,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x19a686070,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406070,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906070,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x19a686068,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406068,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906068,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RDX,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x4ceb88e30,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	stream.c:342-344
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.17 to 7.00 cycles (2.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

7: addition or subtraction

The binary function is loading 140 bytes (17 double precision FP elements). The binary function is storing 84 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	97
loop length	554
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.17 cycles
front end	16.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.00	12.00	12.00	12.00	3.00	10.00	10.00	10.00	0.00	0.00	3.50	3.50	3.50	3.50
cycles	12.00	12.00	12.00	12.00	3.00	10.00	10.00	10.00	0.00	0.00	3.50	3.50	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.17
Dispatch	12.00
Overall L1	16.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.17 cycles. At this rate:

9% of peak load performance is reached (8.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.20 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4030f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88e10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x1c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
MOV -0x28(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4033a1 <main.extracted.50+0x2b1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x19a686060,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334906060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x8,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 403259 <main.extracted.50+0x169>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x38(,%RAX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x3,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $0x7ffffff8,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x6,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4033a1 <main.extracted.50+0x2b1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x404140,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP (%R8,%RDI,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV $0x19a686090,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406090,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906090,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x19a686088,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406088,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906088,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x19a686080,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406080,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906080,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x19a686078,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406078,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906078,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x19a686070,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406070,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906070,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x19a686068,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406068,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x334906068,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDSD (%R8,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RDX,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x4ceb88e30,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.50–	94.71	7.33
○Loop 13 - stream.c:343-344 - exec	94.71	7.24

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