OV - exec - Function main.extracted.45

	Function: main.extracted.45	Module: exec	Source: stream.c:290-292	Coverage (incl. loops): 0.52% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 290 - 292

--------------------------------------------------------------------------------

290: #pragma omp parallel for

291:     for (j = 0; j < STREAM_ARRAY_SIZE; j++)

292: 		a[j] = 2.0E0 * a[j];

0x402ef0 PUSH	%RBP

0x402ef1 MOV	%RSP,%RBP

0x402ef4 PUSH	%RBX

0x402ef5 SUB	$0x28,%RSP

0x402ef9 MOVL	$0,-0xc(%RBP)

0x402f00 MOV	(%RDI),%EBX

0x402f02 MOVQ	$0,-0x20(%RBP)

0x402f0a MOVQ	$0x3344ffff,-0x18(%RBP)

0x402f12 MOVQ	$0x1,-0x28(%RBP)

0x402f1a SUB	$0x8,%RSP

0x402f1e LEA	-0x28(%RBP),%RAX

0x402f22 LEA	-0xc(%RBP),%RCX

0x402f26 MOV	$0x4ceb88db0,%RDI

0x402f30 MOV	$0x401050,%R10

0x402f3a LEA	-0x20(%RBP),%R8

0x402f3e LEA	-0x18(%RBP),%R9

0x402f42 MOV	%EBX,%ESI

0x402f44 MOV	$0x22,%EDX

0x402f49 PUSH	$0x1

0x402f4b PUSH	$0x1

0x402f4d PUSH	%RAX

0x402f4e CALL	%R10

0x402f51 ADD	$0x20,%RSP

0x402f55 MOV	-0x20(%RBP),%RAX

0x402f59 MOV	-0x18(%RBP),%RCX

0x402f5d CMP	%RCX,%RAX

0x402f60 JA	4030d2

0x402f66 MOV	%RCX,%RDX

0x402f69 SUB	%RAX,%RDX

0x402f6c INC	%RDX

0x402f6f CMP	$0x8,%RDX

0x402f73 JB	403007

0x402f79 MOV	$0x406098,%RDI

0x402f83 MOV	%RDX,%RSI

0x402f86 SHR	$0x3,%RSI

0x402f8a LEA	(%RDI,%RAX,8),%RDI

0x402f8e XCHG	%AX,%AX

(12) 0x402f90 VMOVSD	-0x38(%RDI),%XMM0

(12) 0x402f95 VMOVSD	-0x30(%RDI),%XMM1

(12) 0x402f9a VADDSD	%XMM0,%XMM0,%XMM0

(12) 0x402f9e VMOVSD	%XMM0,-0x38(%RDI)

(12) 0x402fa3 VADDSD	%XMM1,%XMM1,%XMM0

(12) 0x402fa7 VMOVSD	%XMM0,-0x30(%RDI)

(12) 0x402fac VMOVSD	-0x28(%RDI),%XMM0

(12) 0x402fb1 VADDSD	%XMM0,%XMM0,%XMM0

(12) 0x402fb5 VMOVSD	%XMM0,-0x28(%RDI)

(12) 0x402fba VMOVSD	-0x20(%RDI),%XMM0

(12) 0x402fbf VADDSD	%XMM0,%XMM0,%XMM0

(12) 0x402fc3 VMOVSD	%XMM0,-0x20(%RDI)

(12) 0x402fc8 VMOVSD	-0x18(%RDI),%XMM0

(12) 0x402fcd VADDSD	%XMM0,%XMM0,%XMM0

(12) 0x402fd1 VMOVSD	%XMM0,-0x18(%RDI)

(12) 0x402fd6 VMOVSD	-0x10(%RDI),%XMM0

(12) 0x402fdb VADDSD	%XMM0,%XMM0,%XMM0

(12) 0x402fdf VMOVSD	%XMM0,-0x10(%RDI)

(12) 0x402fe4 VMOVSD	-0x8(%RDI),%XMM0

(12) 0x402fe9 VADDSD	%XMM0,%XMM0,%XMM0

(12) 0x402fed VMOVSD	%XMM0,-0x8(%RDI)

(12) 0x402ff2 VMOVSD	(%RDI),%XMM0

(12) 0x402ff6 VADDSD	%XMM0,%XMM0,%XMM0

(12) 0x402ffa VMOVSD	%XMM0,(%RDI)

(12) 0x402ffe ADD	$0x40,%RDI

(12) 0x403002 DEC	%RSI

(12) 0x403005 JNE	402f90

0x403007 AND	$0x7ffffff8,%EDX

0x40300d ADD	%RDX,%RAX

0x403010 SUB	%RAX,%RCX

0x403013 CMP	$0x6,%RCX

0x403017 JA	4030d2

0x40301d MOV	$0x404108,%RDX

0x403027 JMP	(%RDX,%RCX,8)

0x40302a MOV	$0x406090,%RCX

0x403034 VMOVSD	(%RCX,%RAX,8),%XMM0

0x403039 VADDSD	%XMM0,%XMM0,%XMM0

0x40303d VMOVSD	%XMM0,(%RCX,%RAX,8)

0x403042 MOV	$0x406088,%RCX

0x40304c VMOVSD	(%RCX,%RAX,8),%XMM0

0x403051 VADDSD	%XMM0,%XMM0,%XMM0

0x403055 VMOVSD	%XMM0,(%RCX,%RAX,8)

0x40305a MOV	$0x406080,%RCX

0x403064 VMOVSD	(%RCX,%RAX,8),%XMM0

0x403069 VADDSD	%XMM0,%XMM0,%XMM0

0x40306d VMOVSD	%XMM0,(%RCX,%RAX,8)

0x403072 MOV	$0x406078,%RCX

0x40307c VMOVSD	(%RCX,%RAX,8),%XMM0

0x403081 VADDSD	%XMM0,%XMM0,%XMM0

0x403085 VMOVSD	%XMM0,(%RCX,%RAX,8)

0x40308a MOV	$0x406070,%RCX

0x403094 VMOVSD	(%RCX,%RAX,8),%XMM0

0x403099 VADDSD	%XMM0,%XMM0,%XMM0

0x40309d VMOVSD	%XMM0,(%RCX,%RAX,8)

0x4030a2 MOV	$0x406068,%RCX

0x4030ac VMOVSD	(%RCX,%RAX,8),%XMM0

0x4030b1 VADDSD	%XMM0,%XMM0,%XMM0

0x4030b5 VMOVSD	%XMM0,(%RCX,%RAX,8)

0x4030ba MOV	$0x406060,%RCX

0x4030c4 VMOVSD	(%RCX,%RAX,8),%XMM0

0x4030c9 VADDSD	%XMM0,%XMM0,%XMM0

0x4030cd VMOVSD	%XMM0,(%RCX,%RAX,8)

0x4030d2 MOV	$0x4ceb88dd0,%RDI

0x4030dc MOV	$0x401030,%RAX

0x4030e6 MOV	%EBX,%ESI

0x4030e8 ADD	$0x28,%RSP

0x4030ec POP	%RBX

0x4030ed POP	%RBP

0x4030ee JMP	%RAX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	stream.c:290-292
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290-292.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.33 to 4.67 cycles (2.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.33 to 1.21 cycles (11.03x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:292

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

7: addition or subtraction

The binary function is loading 84 bytes (10 double precision FP elements). The binary function is storing 84 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	79
nb uops	80
loop length	393
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	8.75	8.75	8.75	8.75	3.00	7.67	7.67	7.67	0.00	0.00	3.50	3.50	3.50	3.50
cycles	8.75	8.75	8.75	8.75	3.00	7.67	7.67	7.67	0.00	0.00	3.50	3.50	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.33
Dispatch	8.75
Overall L1	13.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.33 cycles. At this rate:

6% of peak load performance is reached (6.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (6.30 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.33 to 8.75 cycles (1.52x speedup).

ASM code

In the binary file, the address of the function is: 402ef0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88db0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
MOV -0x18(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
CMP %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4030d2 <main.extracted.45+0x1e2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 403007 <main.extracted.45+0x117>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x406098,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RAX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $0x7ffffff8,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x6,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4030d2 <main.extracted.45+0x1e2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x404108,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP (%RDX,%RCX,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV $0x406090,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406088,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406080,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406078,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406070,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406068,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406060,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x4ceb88dd0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	stream.c:290-292
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.33 to 4.67 cycles (2.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:292

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

7: addition or subtraction

The binary function is loading 84 bytes (10 double precision FP elements). The binary function is storing 84 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	79
nb uops	80
loop length	393
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	8.75	8.75	8.75	8.75	3.00	7.67	7.67	7.67	0.00	0.00	3.50	3.50	3.50	3.50
cycles	8.75	8.75	8.75	8.75	3.00	7.67	7.67	7.67	0.00	0.00	3.50	3.50	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.33
Dispatch	8.75
Overall L1	13.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.33 cycles. At this rate:

6% of peak load performance is reached (6.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (6.30 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402ef0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88db0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
MOV -0x18(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
CMP %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4030d2 <main.extracted.45+0x1e2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 403007 <main.extracted.45+0x117>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x406098,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RAX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $0x7ffffff8,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x6,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4030d2 <main.extracted.45+0x1e2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x404108,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP (%RDX,%RCX,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV $0x406090,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406088,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406080,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406078,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406070,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406068,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x406060,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VADDSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x4ceb88dd0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.45–	0.52	0.04
○Loop 12 - stream.c:291-292 - exec	0.52	0.04

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code