OV - exec - Loop 2

	Loop Id: 2	Module: exec	Source: stream.c:344-344	Coverage: 95.23%

0x40228c VMOVUPD	(%R8,%RCX,1),%ZMM14    [1]

0x402293 VADDPD	(%RDI,%RCX,1),%ZMM14,%ZMM15    [2]

0x40229a VMOVUPD	%ZMM15,(%RSI,%RCX,1)    [3]

0x4022a1 VMOVUPD	0x40(%R8,%RCX,1),%ZMM0    [1]

0x4022a9 VADDPD	0x40(%RDI,%RCX,1),%ZMM0,%ZMM1    [2]

0x4022b1 VMOVUPD	%ZMM1,0x40(%RSI,%RCX,1)    [3]

0x4022b9 VMOVUPD	0x80(%R8,%RCX,1),%ZMM2    [1]

0x4022c1 VADDPD	0x80(%RDI,%RCX,1),%ZMM2,%ZMM3    [2]

0x4022c9 VMOVUPD	%ZMM3,0x80(%RSI,%RCX,1)    [3]

0x4022d1 VMOVUPD	0xc0(%R8,%RCX,1),%ZMM4    [1]

0x4022d9 VADDPD	0xc0(%RDI,%RCX,1),%ZMM4,%ZMM5    [2]

0x4022e1 VMOVUPD	%ZMM5,0xc0(%RSI,%RCX,1)    [3]

0x4022e9 VMOVUPD	0x100(%R8,%RCX,1),%ZMM6    [1]

0x4022f1 VADDPD	0x100(%RDI,%RCX,1),%ZMM6,%ZMM7    [2]

0x4022f9 VMOVUPD	%ZMM7,0x100(%RSI,%RCX,1)    [3]

0x402301 VMOVUPD	0x140(%R8,%RCX,1),%ZMM8    [1]

0x402309 VADDPD	0x140(%RDI,%RCX,1),%ZMM8,%ZMM9    [2]

0x402311 VMOVUPD	%ZMM9,0x140(%RSI,%RCX,1)    [3]

0x402319 VMOVUPD	0x180(%R8,%RCX,1),%ZMM10    [1]

0x402321 VADDPD	0x180(%RDI,%RCX,1),%ZMM10,%ZMM11    [2]

0x402329 VMOVUPD	%ZMM11,0x180(%RSI,%RCX,1)    [3]

0x402331 VMOVUPD	0x1c0(%R8,%RCX,1),%ZMM12    [1]

0x402339 VADDPD	0x1c0(%RDI,%RCX,1),%ZMM12,%ZMM13    [2]

0x402341 VMOVUPD	%ZMM13,0x1c0(%RSI,%RCX,1)    [3]

0x402349 ADD	$0x200,%RCX

0x402350 CMP	%R11,%RCX

0x402353 JNE	40228c

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 344 - 344

--------------------------------------------------------------------------------

344: 	    c[j] = a[j]+b[j];

Coverage (%)	Name	Source Location	Module
○98.94	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.06	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P5, P6, P7,
Function	main._omp_fn.4
Source	stream.c:344-344
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.33
CQA cycles if no scalar integer	13.33
CQA cycles if FP arith vectorized	13.33
CQA cycles if fully vectorized	13.33
Front-end cycles	5.67
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	13.33
P6 cycles	13.33
P7 cycles	13.33
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	34.00
Nb loads	16.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	4.80
Nb FLOP add-sub	64.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	115.20
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P5, P6, P7,
Function	main._omp_fn.4
Source	stream.c:344-344
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.33
CQA cycles if no scalar integer	13.33
CQA cycles if FP arith vectorized	13.33
CQA cycles if fully vectorized	13.33
Front-end cycles	5.67
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	13.33
P6 cycles	13.33
P7 cycles	13.33
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	34.00
Nb loads	16.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	4.80
Nb FLOP add-sub	64.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	115.20
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.4
Source file and lines	stream.c:344-344
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 13.33 to 8.00 cycles (1.67x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

64: addition or subtraction

The binary loop is loading 1024 bytes (128 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	27
nb uops	34
loop length	205
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	0.00	0.00	4.00	4.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	13.33	13.33	13.33	0.00	0.00	8.00	8.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	13.33
Data deps.	1.00
Overall L1	13.33

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.33 cycles. At this rate:

80% of peak load performance is reached (76.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
60% of peak store performance is reached (38.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40228c

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVUPD (%R8,%RCX,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM15,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x40(%R8,%RCX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x40(%RDI,%RCX,1),%ZMM0,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x80(%R8,%RCX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x80(%RDI,%RCX,1),%ZMM2,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM3,0x80(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0xc0(%R8,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0xc0(%RDI,%RCX,1),%ZMM4,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM5,0xc0(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x100(%R8,%RCX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x100(%RDI,%RCX,1),%ZMM6,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM7,0x100(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x140(%R8,%RCX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x140(%RDI,%RCX,1),%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM9,0x140(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x180(%R8,%RCX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x180(%RDI,%RCX,1),%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM11,0x180(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x1c0(%R8,%RCX,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x1c0(%RDI,%RCX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM13,0x1c0(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
ADD $0x200,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 40228c <main._omp_fn.4+0x19c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	main._omp_fn.4
Source file and lines	stream.c:344-344
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 13.33 to 8.00 cycles (1.67x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

64: addition or subtraction

The binary loop is loading 1024 bytes (128 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	27
nb uops	34
loop length	205
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	0.00	0.00	4.00	4.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	13.33	13.33	13.33	0.00	0.00	8.00	8.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.67
Dispatch	13.33
Data deps.	1.00
Overall L1	13.33

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.33 cycles. At this rate:

80% of peak load performance is reached (76.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
60% of peak store performance is reached (38.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40228c

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVUPD (%R8,%RCX,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM14,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM15,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x40(%R8,%RCX,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x40(%RDI,%RCX,1),%ZMM0,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM1,0x40(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x80(%R8,%RCX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x80(%RDI,%RCX,1),%ZMM2,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM3,0x80(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0xc0(%R8,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0xc0(%RDI,%RCX,1),%ZMM4,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM5,0xc0(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x100(%R8,%RCX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x100(%RDI,%RCX,1),%ZMM6,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM7,0x100(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x140(%R8,%RCX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x140(%RDI,%RCX,1),%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM9,0x140(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x180(%R8,%RCX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x180(%RDI,%RCX,1),%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM11,0x180(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
VMOVUPD 0x1c0(%R8,%RCX,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1	vect (100.0%)
VADDPD 0x1c0(%RDI,%RCX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM13,0x1c0(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2	vect (100.0%)
ADD $0x200,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 40228c <main._omp_fn.4+0x19c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code