OV - exec - Function main._omp

	Function: main._omp_fn.4	Module: exec	Source: stream.c:342-344	Coverage (incl. loops): 95.23% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 342 - 344

--------------------------------------------------------------------------------

342: #pragma omp parallel for

343: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

344: 	    c[j] = a[j]+b[j];

0x4020f0 PUSH	%RBP

0x4020f1 MOV	$0x401060,%RAX

0x4020fb MOV	%RSP,%RBP

0x4020fe PUSH	%R14

0x402100 PUSH	%R13

0x402102 PUSH	%R12

0x402104 PUSH	%RBX

0x402105 MOV	$0x401030,%R12

0x40210f AND	$-0x40,%RSP

0x402113 CALL	%RAX

0x402115 MOVSXD	%EAX,%RBX

0x402118 CALL	%R12

0x40211b MOVSXD	%EAX,%RCX

0x40211e MOV	$0x33450000,%EAX

0x402123 CQTO

0x402125 IDIV	%RBX

0x402128 CMP	%RDX,%RCX

0x40212b JL	402410

0x402131 IMUL	%RAX,%RCX

0x402135 ADD	%RCX,%RDX

0x402138 LEA	(%RAX,%RDX,1),%R10

0x40213c CMP	%R10,%RDX

0x40213f JGE	4023ef

0x402145 LEA	-0x1(%RAX),%RSI

0x402149 MOV	%RDX,%RBX

0x40214c CMP	$0x6,%RSI

0x402150 JBE	402420

0x402156 MOV	%RAX,%R11

0x402159 LEA	(,%RDX,8),%RSI

0x402161 MOV	$0x334906100,%R12

0x40216b MOV	$0x19a686100,%R13

0x402175 SHR	$0x3,%R11

0x402179 SAL	$0x6,%R11

0x40217d LEA	-0x40(%R11),%R9

0x402181 MOV	$0x406100,%R14

0x40218b LEA	(%R12,%RSI,1),%RDI

0x40218f LEA	(%R13,%RSI,1),%R8

0x402194 SHR	$0x6,%R9

0x402198 INC	%R9

0x40219b ADD	%R14,%RSI

0x40219e XOR	%ECX,%ECX

0x4021a0 AND	$0x7,%R9D

0x4021a4 JE	40228c

0x4021aa CMP	$0x1,%R9

0x4021ae JE	40226a

0x4021b4 CMP	$0x2,%R9

0x4021b8 JE	402251

0x4021be CMP	$0x3,%R9

0x4021c2 JE	402238

0x4021c4 CMP	$0x4,%R9

0x4021c8 JE	40221f

0x4021ca CMP	$0x5,%R9

0x4021ce JE	402206

0x4021d0 CMP	$0x6,%R9

0x4021d4 JE	4021ed

0x4021d6 VMOVUPD	(%R8),%ZMM0

0x4021dc VADDPD	(%RDI),%ZMM0,%ZMM1

0x4021e2 MOV	$0x40,%ECX

0x4021e7 VMOVUPD	%ZMM1,(%RSI)

0x4021ed VMOVUPD	(%R8,%RCX,1),%ZMM2

0x4021f4 VADDPD	(%RDI,%RCX,1),%ZMM2,%ZMM3

0x4021fb VMOVUPD	%ZMM3,(%RSI,%RCX,1)

0x402202 ADD	$0x40,%RCX

0x402206 VMOVUPD	(%R8,%RCX,1),%ZMM4

0x40220d VADDPD	(%RDI,%RCX,1),%ZMM4,%ZMM5

0x402214 VMOVUPD	%ZMM5,(%RSI,%RCX,1)

0x40221b ADD	$0x40,%RCX

0x40221f VMOVUPD	(%R8,%RCX,1),%ZMM6

0x402226 VADDPD	(%RDI,%RCX,1),%ZMM6,%ZMM7

0x40222d VMOVUPD	%ZMM7,(%RSI,%RCX,1)

0x402234 ADD	$0x40,%RCX

0x402238 VMOVUPD	(%R8,%RCX,1),%ZMM8

0x40223f VADDPD	(%RDI,%RCX,1),%ZMM8,%ZMM9

0x402246 VMOVUPD	%ZMM9,(%RSI,%RCX,1)

0x40224d ADD	$0x40,%RCX

0x402251 VMOVUPD	(%R8,%RCX,1),%ZMM10

0x402258 VADDPD	(%RDI,%RCX,1),%ZMM10,%ZMM11

0x40225f VMOVUPD	%ZMM11,(%RSI,%RCX,1)

0x402266 ADD	$0x40,%RCX

0x40226a VMOVUPD	(%R8,%RCX,1),%ZMM12

0x402271 VADDPD	(%RDI,%RCX,1),%ZMM12,%ZMM13

0x402278 VMOVUPD	%ZMM13,(%RSI,%RCX,1)

0x40227f ADD	$0x40,%RCX

0x402283 CMP	%R11,%RCX

0x402286 JE	402359

(2) 0x40228c VMOVUPD	(%R8,%RCX,1),%ZMM14

(2) 0x402293 VADDPD	(%RDI,%RCX,1),%ZMM14,%ZMM15

(2) 0x40229a VMOVUPD	%ZMM15,(%RSI,%RCX,1)

(2) 0x4022a1 VMOVUPD	0x40(%R8,%RCX,1),%ZMM0

(2) 0x4022a9 VADDPD	0x40(%RDI,%RCX,1),%ZMM0,%ZMM1

(2) 0x4022b1 VMOVUPD	%ZMM1,0x40(%RSI,%RCX,1)

(2) 0x4022b9 VMOVUPD	0x80(%R8,%RCX,1),%ZMM2

(2) 0x4022c1 VADDPD	0x80(%RDI,%RCX,1),%ZMM2,%ZMM3

(2) 0x4022c9 VMOVUPD	%ZMM3,0x80(%RSI,%RCX,1)

(2) 0x4022d1 VMOVUPD	0xc0(%R8,%RCX,1),%ZMM4

(2) 0x4022d9 VADDPD	0xc0(%RDI,%RCX,1),%ZMM4,%ZMM5

(2) 0x4022e1 VMOVUPD	%ZMM5,0xc0(%RSI,%RCX,1)

(2) 0x4022e9 VMOVUPD	0x100(%R8,%RCX,1),%ZMM6

(2) 0x4022f1 VADDPD	0x100(%RDI,%RCX,1),%ZMM6,%ZMM7

(2) 0x4022f9 VMOVUPD	%ZMM7,0x100(%RSI,%RCX,1)

(2) 0x402301 VMOVUPD	0x140(%R8,%RCX,1),%ZMM8

(2) 0x402309 VADDPD	0x140(%RDI,%RCX,1),%ZMM8,%ZMM9

(2) 0x402311 VMOVUPD	%ZMM9,0x140(%RSI,%RCX,1)

(2) 0x402319 VMOVUPD	0x180(%R8,%RCX,1),%ZMM10

(2) 0x402321 VADDPD	0x180(%RDI,%RCX,1),%ZMM10,%ZMM11

(2) 0x402329 VMOVUPD	%ZMM11,0x180(%RSI,%RCX,1)

(2) 0x402331 VMOVUPD	0x1c0(%R8,%RCX,1),%ZMM12

(2) 0x402339 VADDPD	0x1c0(%RDI,%RCX,1),%ZMM12,%ZMM13

(2) 0x402341 VMOVUPD	%ZMM13,0x1c0(%RSI,%RCX,1)

(2) 0x402349 ADD	$0x200,%RCX

(2) 0x402350 CMP	%R11,%RCX

(2) 0x402353 JNE	40228c

0x402359 MOV	%RAX,%RDI

0x40235c AND	$-0x8,%RDI

0x402360 ADD	%RDI,%RDX

0x402363 CMP	%RDI,%RAX

0x402366 JE	402400

0x40236c SUB	%RDI,%RAX

0x40236f LEA	-0x1(%RAX),%RSI

0x402373 CMP	$0x2,%RSI

0x402377 JBE	4023a1

0x402379 ADD	%RBX,%RDI

0x40237c MOV	%RAX,%RBX

0x40237f SAL	$0x3,%RDI

0x402383 VMOVUPD	(%R13,%RDI,1),%YMM14

0x40238a VADDPD	(%R12,%RDI,1),%YMM14,%YMM15

0x402390 AND	$-0x4,%RBX

0x402394 ADD	%RBX,%RDX

0x402397 VMOVUPD	%YMM15,(%R14,%RDI,1)

0x40239d TEST	$0x3,%AL

0x40239f JE	402400

0x4023a1 LEA	0x1(%RDX),%RAX

0x4023a5 VMOVSD	(%R12,%RDX,8),%XMM0

0x4023ab VADDSD	(%R13,%RDX,8),%XMM0,%XMM1

0x4023b2 VMOVSD	%XMM1,(%R14,%RDX,8)

0x4023b8 CMP	%RAX,%R10

0x4023bb JLE	402400

0x4023bd ADD	$0x2,%RDX

0x4023c1 VMOVSD	(%R13,%RAX,8),%XMM2

0x4023c8 VADDSD	(%R12,%RAX,8),%XMM2,%XMM3

0x4023ce VMOVSD	%XMM3,(%R14,%RAX,8)

0x4023d4 CMP	%RDX,%R10

0x4023d7 JLE	402400

0x4023d9 VMOVSD	(%R12,%RDX,8),%XMM4

0x4023df VADDSD	(%R13,%RDX,8),%XMM4,%XMM5

0x4023e6 VMOVSD	%XMM5,(%R14,%RDX,8)

0x4023ec VZEROUPPER

0x4023ef LEA	-0x20(%RBP),%RSP

0x4023f3 POP	%RBX

0x4023f4 POP	%R12

0x4023f6 POP	%R13

0x4023f8 POP	%R14

0x4023fa POP	%RBP

0x4023fb RET

0x4023fc NOPL	(%RAX)

0x402400 VZEROUPPER

0x402403 LEA	-0x20(%RBP),%RSP

0x402407 POP	%RBX

0x402408 POP	%R12

0x40240a POP	%R13

0x40240c POP	%R14

0x40240e POP	%RBP

0x40240f RET

0x402410 INC	%RAX

0x402413 XOR	%EDX,%EDX

0x402415 JMP	402131

0x40241a NOPW	(%RAX,%RAX,1)

0x402420 XOR	%EDI,%EDI

0x402422 MOV	$0x334906100,%R12

0x40242c MOV	$0x19a686100,%R13

0x402436 MOV	$0x406100,%R14

0x402440 JMP	40236c

0x402445 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○98.94	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.06	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:342-344
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342-344.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.33 to 15.67 cycles (1.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 45% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.33 to 20.25 cycles (1.25x speedup).

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342
VMOVUPD: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time). 7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 63 FP arithmetical operations:

63: addition or subtraction

The binary function is loading 1008 bytes (126 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	146
nb uops	152
loop length	659
used x86 registers	15
used mmx registers	0
used xmm registers	6
used ymm registers	2
used zmm registers	14
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.33 cycles
front end	25.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	18.25	18.25	18.25	18.25	12.00	11.67	11.67	11.67	0.00	0.00	5.50	5.50	9.00	9.00
cycles	18.25	18.25	18.25	18.25	12.00	16.33	16.33	16.33	0.00	0.00	9.00	9.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	25.33
Dispatch	18.25
DIV/SQRT	7.00-12.00
Overall L1	25.33

Vectorization ratios

INT

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	72%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	71%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	45%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.33 cycles. At this rate:

41% of peak load performance is reached (39.79 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (19.89 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.33 to 18.25 cycles (1.39x speedup).

ASM code

In the binary file, the address of the function is: 4020f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401030,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL %R12	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 402410 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 4023ef <main._omp_fn.4+0x2ff>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 402420 <main._omp_fn.4+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x3,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SAL $0x6,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x40(%R11),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x406100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R12,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R13,%RSI,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R14,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x7,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 40228c <main._omp_fn.4+0x19c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40226a <main._omp_fn.4+0x17a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402251 <main._omp_fn.4+0x161>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402238 <main._omp_fn.4+0x148>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40221f <main._omp_fn.4+0x12f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402206 <main._omp_fn.4+0x116>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4021ed <main._omp_fn.4+0xfd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R8),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI),%ZMM0,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
MOV $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %ZMM1,(%RSI)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
VMOVUPD (%R8,%RCX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM2,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM4,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM6,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM9,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM11,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM13,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402359 <main._omp_fn.4+0x269>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402400 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 4023a1 <main._omp_fn.4+0x2b1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVUPD (%R13,%RDI,1),%YMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD (%R12,%RDI,1),%YMM14,%YMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
AND $-0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %YMM15,(%R14,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (50.0%)
TEST $0x3,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402400 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R12,%RDX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%R13,%RDX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%R14,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402400 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R13,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%R12,%RAX,8),%XMM2,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,(%R14,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402400 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R12,%RDX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%R13,%RDX,8),%XMM4,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%R14,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 402131 <main._omp_fn.4+0x41>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x334906100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 40236c <main._omp_fn.4+0x27c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:342-344
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342
VMOVUPD: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:344

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 63 FP arithmetical operations:

63: addition or subtraction

The binary function is loading 1008 bytes (126 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	146
nb uops	152
loop length	659
used x86 registers	15
used mmx registers	0
used xmm registers	6
used ymm registers	2
used zmm registers	14
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.33 cycles
front end	25.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	18.25	18.25	18.25	18.25	12.00	11.67	11.67	11.67	0.00	0.00	5.50	5.50	9.00	9.00
cycles	18.25	18.25	18.25	18.25	12.00	16.33	16.33	16.33	0.00	0.00	9.00	9.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	25.33
Dispatch	18.25
DIV/SQRT	7.00-12.00
Overall L1	25.33

Vectorization ratios

INT

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	72%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	72%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	71%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	45%
load	71%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.33 cycles. At this rate:

41% of peak load performance is reached (39.79 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (19.89 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4020f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401030,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
CALL %R12	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %RBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 402410 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 4023ef <main._omp_fn.4+0x2ff>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 402420 <main._omp_fn.4+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x3,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SAL $0x6,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x40(%R11),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x406100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R12,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R13,%RSI,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R14,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x7,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 40228c <main._omp_fn.4+0x19c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40226a <main._omp_fn.4+0x17a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402251 <main._omp_fn.4+0x161>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402238 <main._omp_fn.4+0x148>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40221f <main._omp_fn.4+0x12f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402206 <main._omp_fn.4+0x116>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4021ed <main._omp_fn.4+0xfd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R8),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI),%ZMM0,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
MOV $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %ZMM1,(%RSI)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
VMOVUPD (%R8,%RCX,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM2,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM4,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM6,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM9,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM11,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD (%RDI,%RCX,1),%ZMM12,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM13,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402359 <main._omp_fn.4+0x269>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402400 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 4023a1 <main._omp_fn.4+0x2b1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVUPD (%R13,%RDI,1),%YMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD (%R12,%RDI,1),%YMM14,%YMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50	vect (50.0%)
AND $-0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD %YMM15,(%R14,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (50.0%)
TEST $0x3,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402400 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R12,%RDX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%R13,%RDX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,(%R14,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402400 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R13,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%R12,%RAX,8),%XMM2,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,(%R14,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402400 <main._omp_fn.4+0x310>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R12,%RDX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%R13,%RDX,8),%XMM4,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%R14,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 402131 <main._omp_fn.4+0x41>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x334906100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 40236c <main._omp_fn.4+0x27c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.4–	95.23	7.20
○Loop 2 - stream.c:344-344 - exec	95.23	7.11

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