OV - exec - Function main.extracted.45

	Function: main.extracted.45	Module: exec	Source: stream.c:290-292	Coverage (incl. loops): 0.52% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 290 - 292

--------------------------------------------------------------------------------

290: #pragma omp parallel for

291:     for (j = 0; j < STREAM_ARRAY_SIZE; j++)

292: 		a[j] = 2.0E0 * a[j];

0x403170 PUSH	%RBP

0x403171 MOV	%RSP,%RBP

0x403174 PUSH	%RBX

0x403175 SUB	$0x28,%RSP

0x403179 MOVL	$0,-0xc(%RBP)

0x403180 MOV	(%RDI),%EBX

0x403182 MOVQ	$0,-0x20(%RBP)

0x40318a MOVQ	$0x3344ffff,-0x18(%RBP)

0x403192 MOVQ	$0x1,-0x28(%RBP)

0x40319a SUB	$0x8,%RSP

0x40319e LEA	-0x28(%RBP),%RAX

0x4031a2 MOV	%EBX,%ESI

0x4031a4 MOV	$0x4ceb88dc0,%RDI

0x4031ae MOV	$0x401050,%R10

0x4031b8 LEA	-0xc(%RBP),%RCX

0x4031bc LEA	-0x20(%RBP),%R8

0x4031c0 LEA	-0x18(%RBP),%R9

0x4031c4 MOV	$0x22,%EDX

0x4031c9 PUSH	$0x1

0x4031cb PUSH	$0x1

0x4031cd PUSH	%RAX

0x4031ce CALL	%R10

0x4031d1 ADD	$0x20,%RSP

0x4031d5 MOV	-0x20(%RBP),%RAX

0x4031d9 MOV	-0x18(%RBP),%RSI

0x4031dd CMP	%RSI,%RAX

0x4031e0 JA	40327a

0x4031e6 SUB	%RAX,%RSI

0x4031e9 MOV	$0x406060,%RCX

0x4031f3 INC	%RSI

0x4031f6 MOV	%RSI,%RDX

0x4031f9 AND	$0x7ffffff8,%RDX

0x403200 JE	40323e

0x403202 LEA	(,%RAX,8),%RDI

0x40320a XOR	%R8D,%R8D

0x40320d NOPL	(%RAX)

(12) 0x403210 LEA	(%RDI,%R8,8),%R9

(12) 0x403214 ADD	$0x8,%R8

(12) 0x403218 VMOVUPD	(%RCX,%R9,1),%ZMM0

(12) 0x40321f VADDPD	%ZMM0,%ZMM0,%ZMM0

(12) 0x403225 VMOVUPD	%ZMM0,(%RCX,%R9,1)

(12) 0x40322c CMP	%RDX,%R8

(12) 0x40322f JB	403210

0x403231 CMP	%RDX,%RSI

0x403234 JE	40327a

0x403236 VPBROADCASTQ	%RSI,%ZMM0

0x40323c JMP	403246

0x40323e VPBROADCASTQ	%RSI,%ZMM0

0x403244 XOR	%EDX,%EDX

0x403246 VPBROADCASTQ	%RDX,%ZMM1

0x40324c MOV	$0x404140,%RSI

0x403256 ADD	%RDX,%RAX

0x403259 VPSUBQ	%ZMM1,%ZMM0,%ZMM0

0x40325f VPCMPNLEUQ	(%RSI),%ZMM0,%K1

0x403266 VMOVUPD	(%RCX,%RAX,8),%ZMM0{%K1}{z}

0x40326d VADDPD	%ZMM0,%ZMM0,%ZMM0

0x403273 VMOVUPD	%ZMM0,(%RCX,%RAX,8){%K1}

0x40327a MOV	$0x4ceb88de0,%RDI

0x403284 MOV	$0x401030,%RAX

0x40328e MOV	%EBX,%ESI

0x403290 ADD	$0x28,%RSP

0x403294 POP	%RBX

0x403295 POP	%RBP

0x403296 VZEROUPPER

0x403299 JMP	%RAX

0x40329b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	stream.c:290-292
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290-292.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.17 to 3.17 cycles (3.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 30% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 10.17 to 8.33 cycles (1.22x speedup).

Details

27% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
20% of SSE/AVX stores are used in vector version.
15% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:292
VPBROADCASTQ: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:291
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:291
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary function is loading 148 bytes (18 double precision FP elements). The binary function is storing 92 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	59
nb uops	61
loop length	271
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.17 cycles
front end	10.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.25	6.25	6.25	6.25	3.00	3.33	3.33	3.33	1.00	3.00	3.00	1.00	1.00	1.00
cycles	6.25	6.25	6.25	6.25	3.00	3.67	3.67	3.67	1.00	3.00	3.00	2.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.17
Dispatch	6.25
Overall L1	10.17

Vectorization ratios

INT

all	15%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	27%
load	66%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

INT

all	19%
load	53%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	30%
load	68%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 10.17 cycles. At this rate:

15% of peak load performance is reached (14.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (9.05 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.17 to 6.25 cycles (1.63x speedup).

ASM code

In the binary file, the address of the function is: 403170

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4ceb88dc0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
MOV -0x18(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 40327a <main.extracted.45+0x10a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x406060,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffff8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40323e <main.extracted.45+0xce>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RAX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40327a <main.extracted.45+0x10a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTQ %RSI,%ZMM0	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
JMP 403246 <main.extracted.45+0xd6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VPBROADCASTQ %RSI,%ZMM0	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ %RDX,%ZMM1	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
MOV $0x404140,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VPCMPNLEUQ (%RSI),%ZMM0,%K1																		vect (100.0%)
VMOVUPD (%RCX,%RAX,8),%ZMM0{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD %ZMM0,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM0,(%RCX,%RAX,8){%K1}	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
MOV $0x4ceb88de0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	stream.c:290-292
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.17 to 3.17 cycles (3.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

27% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
20% of SSE/AVX stores are used in vector version.
15% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:292
VPBROADCASTQ: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:291
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:291
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary function is loading 148 bytes (18 double precision FP elements). The binary function is storing 92 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	59
nb uops	61
loop length	271
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.17 cycles
front end	10.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.25	6.25	6.25	6.25	3.00	3.33	3.33	3.33	1.00	3.00	3.00	1.00	1.00	1.00
cycles	6.25	6.25	6.25	6.25	3.00	3.67	3.67	3.67	1.00	3.00	3.00	2.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.17
Dispatch	6.25
Overall L1	10.17

Vectorization ratios

INT

all	15%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	27%
load	66%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

INT

all	19%
load	53%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	30%
load	68%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 10.17 cycles. At this rate:

15% of peak load performance is reached (14.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (9.05 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 403170

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4ceb88dc0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
MOV -0x18(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 40327a <main.extracted.45+0x10a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x406060,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffff8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40323e <main.extracted.45+0xce>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RAX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40327a <main.extracted.45+0x10a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTQ %RSI,%ZMM0	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
JMP 403246 <main.extracted.45+0xd6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VPBROADCASTQ %RSI,%ZMM0	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ %RDX,%ZMM1	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
MOV $0x404140,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VPCMPNLEUQ (%RSI),%ZMM0,%K1																		vect (100.0%)
VMOVUPD (%RCX,%RAX,8),%ZMM0{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VADDPD %ZMM0,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1	vect (100.0%)
VMOVUPD %ZMM0,(%RCX,%RAX,8){%K1}	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
MOV $0x4ceb88de0,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.45–	0.52	0.04
○Loop 12 - stream.c:291-292 - exec	0.52	0.04

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code