| Loop Id: 10 | Module: exec | Source: stream.c:344-344 | Coverage: 96.16% |
|---|
| Loop Id: 10 | Module: exec | Source: stream.c:344-344 | Coverage: 96.16% |
|---|
0x2036f0 VMOVUPD -0xc0(%R10,%R12,8),%ZMM0 [1] |
0x2036f8 VMOVUPD -0x80(%R10,%R12,8),%ZMM1 [1] |
0x203700 VMOVUPD -0x40(%R10,%R12,8),%ZMM2 [1] |
0x203708 VMOVUPD (%R10,%R12,8),%ZMM3 [1] |
0x20370f VADDPD -0xc0(%R11,%R12,8),%ZMM0,%ZMM0 [2] |
0x203717 VADDPD -0x80(%R11,%R12,8),%ZMM1,%ZMM1 [2] |
0x20371f VADDPD -0x40(%R11,%R12,8),%ZMM2,%ZMM2 [2] |
0x203727 VADDPD (%R11,%R12,8),%ZMM3,%ZMM3 [2] |
0x20372e VMOVUPD %ZMM0,-0xc0(%R15,%R12,8) [3] |
0x203736 VMOVUPD %ZMM1,-0x80(%R15,%R12,8) [3] |
0x20373e VMOVUPD %ZMM2,-0x40(%R15,%R12,8) [3] |
0x203746 VMOVUPD %ZMM3,(%R15,%R12,8) [3] |
0x20374d ADD $0x20,%R12 |
0x203751 CMP %R12,%R9 |
0x203754 JNE 2036f0 |
/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 344 - 344 |
-------------------------------------------------------------------------------- |
344: c[j] = a[j]+b[j]; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►99.58+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.67 |
| Bottlenecks | P5, P6, P7, |
| Function | main.omp_outlined.27 |
| Source | stream.c:344-344 |
| Source loop unroll info | unrolled by 32 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 32 |
| CQA cycles | 6.67 |
| CQA cycles if no scalar integer | 6.67 |
| CQA cycles if FP arith vectorized | 6.67 |
| CQA cycles if fully vectorized | 6.67 |
| Front-end cycles | 3.00 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 0.25 |
| P3 cycles | 0.25 |
| P4 cycles | 0.50 |
| P5 cycles | 6.67 |
| P6 cycles | 6.67 |
| P7 cycles | 6.67 |
| P8 cycles | 0.00 |
| P9 cycles | 0.00 |
| P10 cycles | 4.00 |
| P11 cycles | 4.00 |
| P12 cycles | 4.00 |
| P13 cycles | 4.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 15.00 |
| Nb uops | 18.00 |
| Nb loads | 8.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 4.80 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 115.20 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 512.00 |
| Bytes stored | 256.00 |
| Stride 0 | 0.00 |
| Stride 1 | 3.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.67 |
| Bottlenecks | P5, P6, P7, |
| Function | main.omp_outlined.27 |
| Source | stream.c:344-344 |
| Source loop unroll info | unrolled by 32 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 32 |
| CQA cycles | 6.67 |
| CQA cycles if no scalar integer | 6.67 |
| CQA cycles if FP arith vectorized | 6.67 |
| CQA cycles if fully vectorized | 6.67 |
| Front-end cycles | 3.00 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 0.25 |
| P3 cycles | 0.25 |
| P4 cycles | 0.50 |
| P5 cycles | 6.67 |
| P6 cycles | 6.67 |
| P7 cycles | 6.67 |
| P8 cycles | 0.00 |
| P9 cycles | 0.00 |
| P10 cycles | 4.00 |
| P11 cycles | 4.00 |
| P12 cycles | 4.00 |
| P13 cycles | 4.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 15.00 |
| Nb uops | 18.00 |
| Nb loads | 8.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 4.80 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 115.20 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 512.00 |
| Bytes stored | 256.00 |
| Stride 0 | 0.00 |
| Stride 1 | 3.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | main.omp_outlined.27 |
| Source file and lines | stream.c:344-344 |
| Module | exec |
| nb instructions | 15 |
| nb uops | 18 |
| loop length | 102 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 4 |
| nb stack references | 0 |
| micro-operation queue | 3.00 cycles |
| front end | 3.00 cycles |
| ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 4.00 | 4.00 | 4.00 | 0.00 | 0.00 | 2.00 | 2.00 | 4.00 | 4.00 |
| cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 6.67 | 6.67 | 6.67 | 0.00 | 0.00 | 4.00 | 4.00 | 4.00 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 3.00 |
| Dispatch | 6.67 |
| Data deps. | 1.00 |
| Overall L1 | 6.67 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD -0xc0(%R10,%R12,8),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VMOVUPD -0x80(%R10,%R12,8),%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VMOVUPD -0x40(%R10,%R12,8),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VMOVUPD (%R10,%R12,8),%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VADDPD -0xc0(%R11,%R12,8),%ZMM0,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VADDPD -0x80(%R11,%R12,8),%ZMM1,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VADDPD -0x40(%R11,%R12,8),%ZMM2,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VADDPD (%R11,%R12,8),%ZMM3,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VMOVUPD %ZMM0,-0xc0(%R15,%R12,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 | vect (100.0%) |
| VMOVUPD %ZMM1,-0x80(%R15,%R12,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 | vect (100.0%) |
| VMOVUPD %ZMM2,-0x40(%R15,%R12,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 | vect (100.0%) |
| VMOVUPD %ZMM3,(%R15,%R12,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 | vect (100.0%) |
| ADD $0x20,%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP %R12,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| JNE 2036f0 <main.omp_outlined.27+0x110> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
| Function | main.omp_outlined.27 |
| Source file and lines | stream.c:344-344 |
| Module | exec |
| nb instructions | 15 |
| nb uops | 18 |
| loop length | 102 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 4 |
| nb stack references | 0 |
| micro-operation queue | 3.00 cycles |
| front end | 3.00 cycles |
| ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 4.00 | 4.00 | 4.00 | 0.00 | 0.00 | 2.00 | 2.00 | 4.00 | 4.00 |
| cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 6.67 | 6.67 | 6.67 | 0.00 | 0.00 | 4.00 | 4.00 | 4.00 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 3.00 |
| Dispatch | 6.67 |
| Data deps. | 1.00 |
| Overall L1 | 6.67 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD -0xc0(%R10,%R12,8),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VMOVUPD -0x80(%R10,%R12,8),%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VMOVUPD -0x40(%R10,%R12,8),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VMOVUPD (%R10,%R12,8),%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VADDPD -0xc0(%R11,%R12,8),%ZMM0,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VADDPD -0x80(%R11,%R12,8),%ZMM1,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VADDPD -0x40(%R11,%R12,8),%ZMM2,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VADDPD (%R11,%R12,8),%ZMM3,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VMOVUPD %ZMM0,-0xc0(%R15,%R12,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 | vect (100.0%) |
| VMOVUPD %ZMM1,-0x80(%R15,%R12,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 | vect (100.0%) |
| VMOVUPD %ZMM2,-0x40(%R15,%R12,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 | vect (100.0%) |
| VMOVUPD %ZMM3,(%R15,%R12,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 | vect (100.0%) |
| ADD $0x20,%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| CMP %R12,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| JNE 2036f0 <main.omp_outlined.27+0x110> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |