OV - exec - Function main.omp

	Function: main.omp_outlined.27	Module: exec	Source: stream.c:342-344	Coverage (incl. loops): 96.16% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 342 - 344

--------------------------------------------------------------------------------

342: #pragma omp parallel for

343: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

344: 	    c[j] = a[j]+b[j];

0x2035e0 PUSH	%RBP

0x2035e1 MOV	%RSP,%RBP

0x2035e4 PUSH	%R15

0x2035e6 PUSH	%R14

0x2035e8 PUSH	%R13

0x2035ea PUSH	%R12

0x2035ec PUSH	%RBX

0x2035ed SUB	$0x28,%RSP

0x2035f1 MOV	(%RDI),%R14D

0x2035f4 LEA	0x2f4d(%RIP),%RBX

0x2035fb MOVQ	$0,-0x40(%RBP)

0x203603 MOVQ	$0x3344ffff,-0x30(%RBP)

0x20360b MOVQ	$0x1,-0x48(%RBP)

0x203613 MOVL	$0,-0x34(%RBP)

0x20361a SUB	$0x8,%RSP

0x20361e MOV	$0x1148,%RDI

0x203628 LEA	-0x48(%RBP),%RAX

0x20362c LEA	-0x40(%RBP),%R8

0x203630 LEA	-0x34(%RBP),%RCX

0x203634 LEA	-0x30(%RBP),%R9

0x203638 MOV	%R14D,%ESI

0x20363b MOV	$0x22,%EDX

0x203640 ADD	%RBX,%RDI

0x203643 PUSH	$0x1

0x203645 PUSH	$0x1

0x203647 PUSH	%RAX

0x203648 CALL	204350 <@plt_start@+0x80>

0x20364d ADD	$0x20,%RSP

0x203651 MOV	-0x30(%RBP),%RCX

0x203655 MOV	-0x40(%RBP),%R8

0x203659 MOV	$0x3344ffff,%EAX

0x20365e CMP	$0x3344ffff,%RCX

0x203665 CMOVL	%RCX,%RAX

0x203669 MOV	%RAX,-0x30(%RBP)

0x20366d CMP	%RAX,%R8

0x203670 JG	2037dd

0x203676 MOV	%RAX,%RDI

0x203679 SUB	%R8,%RDI

0x20367c MOV	$0x1198,%RCX

0x203686 MOV	$0x19a281198,%RDX

0x203690 MOV	$0x334501198,%RSI

0x20369a INC	%RDI

0x20369d CMP	$0x4,%RDI

0x2036a1 JAE	2036ab

0x2036a3 MOV	%R8,%R10

0x2036a6 JMP	2037b0

0x2036ab CMP	$0x20,%RDI

0x2036af JAE	2036b9

0x2036b1 XOR	%R9D,%R9D

0x2036b4 JMP	203769

0x2036b9 LEA	(%RBX,%RCX,1),%R10

0x2036bd LEA	(%RBX,%RDX,1),%R11

0x2036c1 LEA	(%RBX,%RSI,1),%R15

0x2036c5 MOV	%RDI,%R9

0x2036c8 AND	$-0x20,%R9

0x2036cc XOR	%R12D,%R12D

0x2036cf LEA	0xc0(%R10,%R8,8),%R10

0x2036d7 LEA	0xc0(%R11,%R8,8),%R11

0x2036df LEA	0xc0(%R15,%R8,8),%R15

0x2036e7 NOPW	(%RAX,%RAX,1)

(10) 0x2036f0 VMOVUPD	-0xc0(%R10,%R12,8),%ZMM0

(10) 0x2036f8 VMOVUPD	-0x80(%R10,%R12,8),%ZMM1

(10) 0x203700 VMOVUPD	-0x40(%R10,%R12,8),%ZMM2

(10) 0x203708 VMOVUPD	(%R10,%R12,8),%ZMM3

(10) 0x20370f VADDPD	-0xc0(%R11,%R12,8),%ZMM0,%ZMM0

(10) 0x203717 VADDPD	-0x80(%R11,%R12,8),%ZMM1,%ZMM1

(10) 0x20371f VADDPD	-0x40(%R11,%R12,8),%ZMM2,%ZMM2

(10) 0x203727 VADDPD	(%R11,%R12,8),%ZMM3,%ZMM3

(10) 0x20372e VMOVUPD	%ZMM0,-0xc0(%R15,%R12,8)

(10) 0x203736 VMOVUPD	%ZMM1,-0x80(%R15,%R12,8)

(10) 0x20373e VMOVUPD	%ZMM2,-0x40(%R15,%R12,8)

(10) 0x203746 VMOVUPD	%ZMM3,(%R15,%R12,8)

(10) 0x20374d ADD	$0x20,%R12

(10) 0x203751 CMP	%R12,%R9

(10) 0x203754 JNE	2036f0

0x203756 CMP	%R9,%RDI

0x203759 JE	2037dd

0x20375f TEST	$0x1c,%DIL

0x203763 JE	203807

0x203769 MOV	%RDI,%R11

0x20376c LEA	(%RBX,%RCX,1),%R15

0x203770 LEA	(%RBX,%RDX,1),%R12

0x203774 AND	$-0x4,%R11

0x203778 LEA	(%RBX,%RSI,1),%R13

0x20377c LEA	(%R8,%R11,1),%R10

0x203780 LEA	(%R15,%R8,8),%R15

0x203784 LEA	(%R12,%R8,8),%R12

0x203788 LEA	(%R13,%R8,8),%R8

0x20378d NOPL	(%RAX)

(12) 0x203790 VMOVUPD	(%R15,%R9,8),%YMM0

(12) 0x203796 VADDPD	(%R12,%R9,8),%YMM0,%YMM0

(12) 0x20379c VMOVUPD	%YMM0,(%R8,%R9,8)

(12) 0x2037a2 ADD	$0x4,%R9

(12) 0x2037a6 CMP	%R9,%R11

(12) 0x2037a9 JNE	203790

0x2037ab CMP	%R11,%RDI

0x2037ae JE	2037dd

0x2037b0 DEC	%R10

0x2037b3 ADD	%RBX,%RCX

0x2037b6 ADD	%RBX,%RDX

0x2037b9 ADD	%RBX,%RSI

0x2037bc NOPL	(%RAX)

(11) 0x2037c0 VMOVSD	0x8(%RCX,%R10,8),%XMM0

(11) 0x2037c7 VADDSD	0x8(%RDX,%R10,8),%XMM0,%XMM0

(11) 0x2037ce VMOVSD	%XMM0,0x8(%RSI,%R10,8)

(11) 0x2037d5 INC	%R10

(11) 0x2037d8 CMP	%RAX,%R10

(11) 0x2037db JL	2037c0

0x2037dd MOV	$0x1160,%RAX

0x2037e7 MOV	%R14D,%ESI

0x2037ea ADD	%RAX,%RBX

0x2037ed MOV	%RBX,%RDI

0x2037f0 VZEROUPPER

0x2037f3 CALL	204370 <@plt_start@+0xa0>

0x2037f8 ADD	$0x28,%RSP

0x2037fc POP	%RBX

0x2037fd POP	%R12

0x2037ff POP	%R13

0x203801 POP	%R14

0x203803 POP	%R15

0x203805 POP	%RBP

0x203806 RET

0x203807 ADD	%R9,%R8

0x20380a JMP	2036a3

0x20380f NOP

Coverage (%)	Name	Source Location	Module
►99.58+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:342-344
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342-344.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.50 to 1.18 cycles (14.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	98
nb uops	99
loop length	402
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	13.50	13.50	13.50	13.50	6.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	13.50	13.50	13.50	13.50	6.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.50
Dispatch	13.50
Overall L1	16.50

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.50 cycles. At this rate:

1% of peak load performance is reached (1.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.18 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.50 to 13.50 cycles (1.22x speedup).

ASM code

In the binary file, the address of the function is: 2035e0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
LEA 0x2f4d(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x1148,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204350 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	1	0.50	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
CMP %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JG 2037dd <main.omp_outlined.27+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x1198,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a281198,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334501198,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x4,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 2036ab <main.omp_outlined.27+0xcb>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 2037b0 <main.omp_outlined.27+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
CMP $0x20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 2036b9 <main.omp_outlined.27+0xd9>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 203769 <main.omp_outlined.27+0x189>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
LEA (%RBX,%RCX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R10,%R8,8),%R10	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA 0xc0(%R11,%R8,8),%R11	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA 0xc0(%R15,%R8,8),%R15	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 2037dd <main.omp_outlined.27+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
TEST $0x1c,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JE 203807 <main.omp_outlined.27+0x227>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RCX,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
AND $-0x4,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R8,%R11,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R15,%R8,8),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R12,%R8,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R13,%R8,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R11,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 2037dd <main.omp_outlined.27+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
DEC %R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x1160,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204370 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
ADD %R9,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JMP 2036a3 <main.omp_outlined.27+0xc3>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:342-344
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:342

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	98
nb uops	99
loop length	402
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	13.50	13.50	13.50	13.50	6.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	13.50	13.50	13.50	13.50	6.00	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.50
Dispatch	13.50
Overall L1	16.50

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.50 cycles. At this rate:

1% of peak load performance is reached (1.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.18 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 2035e0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
LEA 0x2f4d(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x1148,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204350 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	1	0.50	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
CMP %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JG 2037dd <main.omp_outlined.27+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x1198,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a281198,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334501198,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x4,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 2036ab <main.omp_outlined.27+0xcb>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 2037b0 <main.omp_outlined.27+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
CMP $0x20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 2036b9 <main.omp_outlined.27+0xd9>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 203769 <main.omp_outlined.27+0x189>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
LEA (%RBX,%RCX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RDI,%R9	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R10,%R8,8),%R10	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA 0xc0(%R11,%R8,8),%R11	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
LEA 0xc0(%R15,%R8,8),%R15	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 2037dd <main.omp_outlined.27+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
TEST $0x1c,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JE 203807 <main.omp_outlined.27+0x227>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%RCX,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
AND $-0x4,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R8,%R11,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R15,%R8,8),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R12,%R8,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R13,%R8,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R11,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 2037dd <main.omp_outlined.27+0x1fd>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
DEC %R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x1160,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204370 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
ADD %R9,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JMP 2036a3 <main.omp_outlined.27+0xc3>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.27–	96.16	7.23
○Loop 10 - stream.c:344-344 - exec	96.16	7.11
○Loop 11 - stream.c:343-344 - exec	0.00	0.00
○Loop 12 - stream.c:344-344 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code