OV - exec - Function main.omp

	Function: main.omp_outlined.18	Module: exec	Source: stream.c:290-292	Coverage (incl. loops): 0.52% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c: 290 - 292

--------------------------------------------------------------------------------

290: #pragma omp parallel for

291:     for (j = 0; j < STREAM_ARRAY_SIZE; j++)

292: 		a[j] = 2.0E0 * a[j];

0x203420 PUSH	%RBP

0x203421 MOV	%RSP,%RBP

0x203424 PUSH	%R14

0x203426 PUSH	%RBX

0x203427 SUB	$0x20,%RSP

0x20342b MOV	(%RDI),%R14D

0x20342e LEA	0x3113(%RIP),%RBX

0x203435 MOVQ	$0,-0x28(%RBP)

0x20343d MOVQ	$0x3344ffff,-0x18(%RBP)

0x203445 MOVQ	$0x1,-0x30(%RBP)

0x20344d MOVL	$0,-0x1c(%RBP)

0x203454 SUB	$0x8,%RSP

0x203458 MOV	$0x1100,%RDI

0x203462 LEA	-0x30(%RBP),%RAX

0x203466 LEA	-0x1c(%RBP),%RCX

0x20346a LEA	-0x28(%RBP),%R8

0x20346e LEA	-0x18(%RBP),%R9

0x203472 MOV	%R14D,%ESI

0x203475 MOV	$0x22,%EDX

0x20347a ADD	%RBX,%RDI

0x20347d PUSH	$0x1

0x20347f PUSH	$0x1

0x203481 PUSH	%RAX

0x203482 CALL	204350 <@plt_start@+0x80>

0x203487 ADD	$0x20,%RSP

0x20348b MOV	-0x18(%RBP),%RCX

0x20348f MOV	$0x3344ffff,%EAX

0x203494 CMP	$0x3344ffff,%RCX

0x20349b CMOVL	%RCX,%RAX

0x20349f MOV	-0x28(%RBP),%RCX

0x2034a3 MOV	%RAX,-0x18(%RBP)

0x2034a7 CMP	%RAX,%RCX

0x2034aa JG	2035b8

0x2034b0 MOV	%RAX,%RSI

0x2034b3 SUB	%RCX,%RSI

0x2034b6 MOV	$0x1198,%RDX

0x2034c0 INC	%RSI

0x2034c3 CMP	$0x4,%RSI

0x2034c7 JB	203593

0x2034cd CMP	$0x20,%RSI

0x2034d1 JAE	2034da

0x2034d3 XOR	%EDI,%EDI

0x2034d5 JMP	20355a

0x2034da LEA	(%RBX,%RDX,1),%R8

0x2034de MOV	%RSI,%RDI

0x2034e1 AND	$-0x20,%RDI

0x2034e5 XOR	%R9D,%R9D

0x2034e8 LEA	0xc0(%R8,%RCX,8),%R8

(8) 0x2034f0 VMOVUPD	-0xc0(%R8,%R9,8),%ZMM0

(8) 0x2034f8 VMOVUPD	-0x80(%R8,%R9,8),%ZMM1

(8) 0x203500 VMOVUPD	-0x40(%R8,%R9,8),%ZMM2

(8) 0x203508 VMOVUPD	(%R8,%R9,8),%ZMM3

(8) 0x20350f VADDPD	%ZMM0,%ZMM0,%ZMM0

(8) 0x203515 VADDPD	%ZMM1,%ZMM1,%ZMM1

(8) 0x20351b VADDPD	%ZMM2,%ZMM2,%ZMM2

(8) 0x203521 VADDPD	%ZMM3,%ZMM3,%ZMM3

(8) 0x203527 VMOVUPD	%ZMM0,-0xc0(%R8,%R9,8)

(8) 0x20352f VMOVUPD	%ZMM1,-0x80(%R8,%R9,8)

(8) 0x203537 VMOVUPD	%ZMM2,-0x40(%R8,%R9,8)

(8) 0x20353f VMOVUPD	%ZMM3,(%R8,%R9,8)

(8) 0x203546 ADD	$0x20,%R9

(8) 0x20354a CMP	%R9,%RDI

(8) 0x20354d JNE	2034f0

0x20354f CMP	%RDI,%RSI

0x203552 JE	2035b8

0x203554 TEST	$0x1c,%SIL

0x203558 JE	203590

0x20355a LEA	(%RBX,%RDX,1),%R9

0x20355e MOV	%RSI,%R8

0x203561 AND	$-0x4,%R8

0x203565 LEA	(%R9,%RCX,8),%R9

0x203569 ADD	%R8,%RCX

0x20356c NOPL	(%RAX)

(9) 0x203570 VMOVUPD	(%R9,%RDI,8),%YMM0

(9) 0x203576 VADDPD	%YMM0,%YMM0,%YMM0

(9) 0x20357a VMOVUPD	%YMM0,(%R9,%RDI,8)

(9) 0x203580 ADD	$0x4,%RDI

(9) 0x203584 CMP	%RDI,%R8

(9) 0x203587 JNE	203570

0x203589 CMP	%R8,%RSI

0x20358c JNE	203593

0x20358e JMP	2035b8

0x203590 ADD	%RDI,%RCX

0x203593 DEC	%RCX

0x203596 ADD	%RBX,%RDX

0x203599 NOPL	(%RAX)

(7) 0x2035a0 VMOVSD	0x8(%RDX,%RCX,8),%XMM0

(7) 0x2035a6 VADDSD	%XMM0,%XMM0,%XMM0

(7) 0x2035aa VMOVSD	%XMM0,0x8(%RDX,%RCX,8)

(7) 0x2035b0 INC	%RCX

(7) 0x2035b3 CMP	%RAX,%RCX

(7) 0x2035b6 JL	2035a0

0x2035b8 MOV	$0x1118,%RAX

0x2035c2 MOV	%R14D,%ESI

0x2035c5 ADD	%RAX,%RBX

0x2035c8 MOV	%RBX,%RDI

0x2035cb VZEROUPPER

0x2035ce CALL	204370 <@plt_start@+0xa0>

0x2035d3 ADD	$0x20,%RSP

0x2035d7 POP	%RBX

0x2035d8 POP	%R14

0x2035da POP	%RBP

0x2035db RET

0x2035dc NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►98.91+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
►1.09+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	unknown kernel region	unknown kernel region	kernel

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:290-292
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290-292.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.83 to 0.93 cycles (13.84x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	77
nb uops	77
loop length	304
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.83 cycles
front end	12.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.50	10.50	10.25	10.25	5.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.50	10.50	10.25	10.25	5.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.83
Dispatch	10.50
Overall L1	12.83

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

all	10%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.83 cycles. At this rate:

1% of peak load performance is reached (1.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.81 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.83 to 10.50 cycles (1.22x speedup).

ASM code

In the binary file, the address of the function is: 203420

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
LEA 0x3113(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x1100,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x1c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204350 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x18(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	1	0.50	N/A
MOV -0x28(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
CMP %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JG 2035b8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x1198,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMP $0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 203593 <main.omp_outlined.18+0x173>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
CMP $0x20,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 2034da <main.omp_outlined.18+0xba>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 20355a <main.omp_outlined.18+0x13a>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
LEA (%RBX,%RDX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R8,%RCX,8),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
CMP %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 2035b8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
TEST $0x1c,%SIL	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JE 203590 <main.omp_outlined.18+0x170>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA (%RBX,%RDX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R9,%RCX,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 203593 <main.omp_outlined.18+0x173>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 2035b8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
DEC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x1118,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204370 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:290-292
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/ins01.benchmarkcenter.megware.com/177-374-0840/stream-add/build/stream-add/src/stream.c:290

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	77
nb uops	77
loop length	304
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.83 cycles
front end	12.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.50	10.50	10.25	10.25	5.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.50	10.50	10.25	10.25	5.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.83
Dispatch	10.50
Overall L1	12.83

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

all	10%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.83 cycles. At this rate:

1% of peak load performance is reached (1.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.81 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 203420

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
LEA 0x3113(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVL $0,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x1100,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x1c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 204350 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x18(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	1	0.50	N/A
MOV -0x28(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV %RAX,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
CMP %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JG 2035b8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x1198,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
CMP $0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 203593 <main.omp_outlined.18+0x173>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
CMP $0x20,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JAE 2034da <main.omp_outlined.18+0xba>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 20355a <main.omp_outlined.18+0x13a>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
LEA (%RBX,%RDX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA 0xc0(%R8,%RCX,8),%R8	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50	N/A
CMP %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 2035b8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
TEST $0x1c,%SIL	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JE 203590 <main.omp_outlined.18+0x170>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA (%RBX,%RDX,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA (%R9,%RCX,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 203593 <main.omp_outlined.18+0x173>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
JMP 2035b8 <main.omp_outlined.18+0x198>	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
DEC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x1118,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 204370 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.18–	0.52	0.04
○Loop 8 - stream.c:292-292 - exec	0.52	0.04
○Loop 7 - stream.c:291-292 - exec	0.00	0.00
○Loop 9 - stream.c:292-292 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code