OV - exec - Loop 10

	Loop Id: 10	Module: exec	Source: stream.c:322-324	Coverage: 0.00%

0x4017a0 MADD	X14, X2, X0, X3

0x4017a4 ADD	X11, X2, X14

0x4017a8 CMP	X14, X11

0x4017ac B.GE	4018bc

0x4017b0 ADRP	X5, 4017b0

0x4017b4 SUB	X4, X11, X14

0x4017b8 LDR	X6, [X5, #2264]

0x4017bc ANDS	X7, X4, #4224

0x4017c0 LDP	X12, X13, [X6, #8]

0x4017c4 B.EQ	401854

0x4017c8 CMP	X7, #1

0x4017cc B.EQ	401840

0x4017d0 CMP	X7, #2

0x4017d4 B.EQ	401834

0x4017d8 CMP	X7, #3

0x4017dc B.EQ	401828

0x4017e0 CMP	X7, #4

0x4017e4 B.EQ	40181c

0x4017e8 CMP	X7, #5

0x4017ec B.EQ	401810

0x4017f0 CMP	X7, #6

0x4017f4 B.EQ	401804

0x4017f8 LDR	D31, [X13, X14,LSL #3]

0x4017fc STR	D31, [X12, X14,LSL #3]

0x401800 ADD	X14, X14, #1

0x401804 LDR	D0, [X13, X14,LSL #3]

0x401808 STR	D0, [X12, X14,LSL #3]

0x40180c ADD	X14, X14, #1

0x401810 LDR	D1, [X13, X14,LSL #3]

0x401814 STR	D1, [X12, X14,LSL #3]

0x401818 ADD	X14, X14, #1

0x40181c LDR	D2, [X13, X14,LSL #3]

0x401820 STR	D2, [X12, X14,LSL #3]

0x401824 ADD	X14, X14, #1

0x401828 LDR	D3, [X13, X14,LSL #3]

0x40182c STR	D3, [X12, X14,LSL #3]

0x401830 ADD	X14, X14, #1

0x401834 LDR	D4, [X13, X14,LSL #3]

0x401838 STR	D4, [X12, X14,LSL #3]

0x40183c ADD	X14, X14, #1

0x401840 LDR	D5, [X13, X14,LSL #3]

0x401844 STR	D5, [X12, X14,LSL #3]

0x401848 ADD	X14, X14, #1

0x40184c CMP	X11, X14

0x401850 B.EQ	4018bc

  (11) 0x401854 LDR	D6, [X13, X14,LSL #3]

  (11) 0x401858 ADD	X15, X14, #1

  (11) 0x40185c ADD	X10, X14, #2

  (11) 0x401860 ADD	X9, X14, #3

  (11) 0x401864 ADD	X8, X14, #4

  (11) 0x401868 ADD	X16, X14, #5

  (11) 0x40186c ADD	X17, X14, #6

  (11) 0x401870 ADD	X18, X14, #7

  (11) 0x401874 STR	D6, [X12, X14,LSL #3]

  (11) 0x401878 ADD	X14, X14, #8

  (11) 0x40187c LDR	D7, [X13, X15,LSL #3]

  (11) 0x401880 STR	D7, [X12, X15,LSL #3]

  (11) 0x401884 LDR	D16, [X13, X10,LSL #3]

  (11) 0x401888 STR	D16, [X12, X10,LSL #3]

  (11) 0x40188c LDR	D17, [X13, X9,LSL #3]

  (11) 0x401890 STR	D17, [X12, X9,LSL #3]

  (11) 0x401894 LDR	D18, [X13, X8,LSL #3]

  (11) 0x401898 STR	D18, [X12, X8,LSL #3]

  (11) 0x40189c LDR	D19, [X13, X16,LSL #3]

  (11) 0x4018a0 STR	D19, [X12, X16,LSL #3]

  (11) 0x4018a4 LDR	D20, [X13, X17,LSL #3]

  (11) 0x4018a8 STR	D20, [X12, X17,LSL #3]

  (11) 0x4018ac LDR	D21, [X13, X18,LSL #3]

  (11) 0x4018b0 STR	D21, [X12, X18,LSL #3]

  (11) 0x4018b4 CMP	X11, X14

  (11) 0x4018b8 B.NE	401854

0x4018bc LDR	X19, [SP, #16]

0x4018c0 LDP	X29, X30, [SP], #32

0x4018c4 RET

0x4018c8 ADD	X2, X2, #1

0x4018cc MOVZ	X3, #0

0x4018d0 B	4017a0

/home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c: 322 - 324

--------------------------------------------------------------------------------

322: #pragma omp parallel for

323: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

324: 	    c[j] = a[j];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.32
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	main._omp_fn.4
Source	stream.c:322-324
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.38
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	6.38
CQA cycles if fully vectorized	5.50
Front-end cycles	6.38
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.58
P7 cycles	3.58
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	6.17
P13 cycles	5.83
P14 cycles	6.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	51.00
Nb loads	NA
Nb stores	7.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.10
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	51.79
Vector-efficiency ratio load	55.56
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.32
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	main._omp_fn.4
Source	stream.c:322-324
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.38
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	6.38
CQA cycles if fully vectorized	5.50
Front-end cycles	6.38
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.58
P7 cycles	3.58
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	6.17
P13 cycles	5.83
P14 cycles	6.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	51.00
Nb loads	NA
Nb stores	7.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.10
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	51.79
Vector-efficiency ratio load	55.56
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.4
Source file and lines	stream.c:322-324
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:322-324.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.38 to 4.83 cycles (1.32x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 51% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.38 to 5.50 cycles (1.16x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	51
nb uops	51
loop length	204
used w registers	0
used x registers	14
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.50	5.50	3.75	3.75	3.67	3.67	3.58	3.58	3.50	3.50	0.00	0.00	6.17	5.83	6.00	0.00	0.00
cycles	5.50	5.50	3.75	3.75	3.67	3.67	3.58	3.58	3.50	3.50	0.00	0.00	6.17	5.83	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Dispatch	6.17
Overall L1	6.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	51%
load	55%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.38 cycles. At this rate:

16% of peak load performance is reached (16.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4018c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
MADD X14, X2, X0, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X11, X2, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X14, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4018bc <main._omp_fn.4+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, 4017b0 <main._omp_fn.4+0x40>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X4, X11, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X6, [X5, #2264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ANDS X7, X4, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
LDP X12, X13, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
B.EQ 401854 <main._omp_fn.4+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401840 <main._omp_fn.4+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401834 <main._omp_fn.4+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401828 <main._omp_fn.4+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40181c <main._omp_fn.4+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401810 <main._omp_fn.4+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401804 <main._omp_fn.4+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D31, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D0, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D0, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D1, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D1, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D2, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D2, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D3, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D3, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D4, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D4, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D5, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D5, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X11, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4018bc <main._omp_fn.4+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
B 4017a0 <main._omp_fn.4+0x30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.4
Source file and lines	stream.c:322-324
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:322-324.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.38 to 4.83 cycles (1.32x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	51
nb uops	51
loop length	204
used w registers	0
used x registers	14
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.50	5.50	3.75	3.75	3.67	3.67	3.58	3.58	3.50	3.50	0.00	0.00	6.17	5.83	6.00	0.00	0.00
cycles	5.50	5.50	3.75	3.75	3.67	3.67	3.58	3.58	3.50	3.50	0.00	0.00	6.17	5.83	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Dispatch	6.17
Overall L1	6.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	51%
load	55%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.38 cycles. At this rate:

16% of peak load performance is reached (16.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4018c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
MADD X14, X2, X0, X3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X11, X2, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X14, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4018bc <main._omp_fn.4+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, 4017b0 <main._omp_fn.4+0x40>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X4, X11, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X6, [X5, #2264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ANDS X7, X4, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
LDP X12, X13, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
B.EQ 401854 <main._omp_fn.4+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401840 <main._omp_fn.4+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401834 <main._omp_fn.4+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401828 <main._omp_fn.4+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40181c <main._omp_fn.4+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401810 <main._omp_fn.4+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401804 <main._omp_fn.4+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D31, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D0, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D0, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D1, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D1, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D2, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D2, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D3, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D3, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D4, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D4, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D5, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D5, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X14, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X11, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4018bc <main._omp_fn.4+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
B 4017a0 <main._omp_fn.4+0x30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code