OV - exec - Loop 4

	Loop Id: 4	Module: exec	Source: stream.c:358-360	Coverage: 0.00%

0x4011d4 MADD	X1, X5, X1, X0

0x4011d8 ADD	X12, X5, X1

0x4011dc CMP	X1, X12

0x4011e0 B.GE	4013dc

0x4011e4 ADRP	X3, 4011e4

0x4011e8 SUB	X4, X5, #1

0x4011ec LDR	D31, [X20]

0x4011f0 LDR	X6, [X3, #1392]

0x4011f4 LDR	X10, [X6, #16]

0x4011f8 LDP	X8, X9, [X6]

0x4011fc CMP	X4, #1

0x401200 B.LS	4013f4

0x401204 UBFM	X11, X1, #61, #60

0x401208 ADD	X17, X10, X1,LSL #3

0x40120c ADD	X7, X11, #8

0x401210 ADD	X13, X8, X7

0x401214 ADD	X14, X9, X7

0x401218 CMP	X13, X17

0x40121c CCMP	X14, X17, #4, #1

0x401220 B.EQ	4013f4

0x401224 UBFM	X15, X5, #1, #63

0x401228 DUP	V30.2D, V31.D[0]

0x40122c ADD	X18, X8, X11

0x401230 UBFM	X30, X15, #60, #59

0x401234 MOVZ	X0, #0

0x401238 SUB	X16, X30, #16

0x40123c ADD	X20, X9, X11

0x401240 UBFM	X19, X16, #4, #63

0x401244 ADD	X2, X19, #1

0x401248 ANDS	X12, X2, #4224

0x40124c B.EQ	401314

0x401250 CMP	X12, #1

0x401254 B.EQ	4012f8

0x401258 CMP	X12, #2

0x40125c B.EQ	4012e4

0x401260 CMP	X12, #3

0x401264 B.EQ	4012d0

0x401268 CMP	X12, #4

0x40126c B.EQ	4012bc

0x401270 CMP	X12, #5

0x401274 B.EQ	4012a8

0x401278 CMP	X12, #6

0x40127c B.EQ	401294

0x401280 LDR	Q23, [X20]

0x401284 MOVZ	X0, #16

0x401288 LDR	Q22, [X18]

0x40128c FMLA	V22.2D, V23.2D, V30.2D

0x401290 STR	Q22, [X17]

0x401294 LDR	Q21, [X20, X0]

0x401298 LDR	Q20, [X18, X0]

0x40129c FMLA	V20.2D, V21.2D, V30.2D

0x4012a0 STR	Q20, [X17, X0]

0x4012a4 ADD	X0, X0, #16

0x4012a8 LDR	Q19, [X20, X0]

0x4012ac LDR	Q18, [X18, X0]

0x4012b0 FMLA	V18.2D, V19.2D, V30.2D

0x4012b4 STR	Q18, [X17, X0]

0x4012b8 ADD	X0, X0, #16

0x4012bc LDR	Q17, [X20, X0]

0x4012c0 LDR	Q16, [X18, X0]

0x4012c4 FMLA	V16.2D, V17.2D, V30.2D

0x4012c8 STR	Q16, [X17, X0]

0x4012cc ADD	X0, X0, #16

0x4012d0 LDR	Q7, [X20, X0]

0x4012d4 LDR	Q6, [X18, X0]

0x4012d8 FMLA	V6.2D, V7.2D, V30.2D

0x4012dc STR	Q6, [X17, X0]

0x4012e0 ADD	X0, X0, #16

0x4012e4 LDR	Q5, [X20, X0]

0x4012e8 LDR	Q4, [X18, X0]

0x4012ec FMLA	V4.2D, V5.2D, V30.2D

0x4012f0 STR	Q4, [X17, X0]

0x4012f4 ADD	X0, X0, #16

0x4012f8 LDR	Q3, [X20, X0]

0x4012fc LDR	Q2, [X18, X0]

0x401300 FMLA	V2.2D, V3.2D, V30.2D

0x401304 STR	Q2, [X17, X0]

0x401308 ADD	X0, X0, #16

0x40130c CMP	X30, X0

0x401310 B.EQ	4013bc

  (6) 0x401314 LDR	Q1, [X20, X0]

  (6) 0x401318 ADD	X3, X0, #16

  (6) 0x40131c ADD	X6, X0, #32

  (6) 0x401320 ADD	X4, X0, #48

  (6) 0x401324 ADD	X7, X0, #64

  (6) 0x401328 LDR	Q0, [X18, X0]

  (6) 0x40132c ADD	X13, X0, #80

  (6) 0x401330 ADD	X14, X0, #96

  (6) 0x401334 ADD	X11, X0, #112

  (6) 0x401338 FMLA	V0.2D, V1.2D, V30.2D

  (6) 0x40133c STR	Q0, [X17, X0]

  (6) 0x401340 ADD	X0, X0, #128

  (6) 0x401344 LDR	Q29, [X20, X3]

  (6) 0x401348 LDR	Q28, [X18, X3]

  (6) 0x40134c FMLA	V28.2D, V29.2D, V30.2D

  (6) 0x401350 STR	Q28, [X17, X3]

  (6) 0x401354 LDR	Q27, [X20, X6]

  (6) 0x401358 LDR	Q26, [X18, X6]

  (6) 0x40135c FMLA	V26.2D, V27.2D, V30.2D

  (6) 0x401360 STR	Q26, [X17, X6]

  (6) 0x401364 LDR	Q25, [X20, X4]

  (6) 0x401368 LDR	Q24, [X18, X4]

  (6) 0x40136c FMLA	V24.2D, V25.2D, V30.2D

  (6) 0x401370 STR	Q24, [X17, X4]

  (6) 0x401374 LDR	Q23, [X20, X7]

  (6) 0x401378 LDR	Q22, [X18, X7]

  (6) 0x40137c FMLA	V22.2D, V23.2D, V30.2D

  (6) 0x401380 STR	Q22, [X17, X7]

  (6) 0x401384 LDR	Q21, [X20, X13]

  (6) 0x401388 LDR	Q20, [X18, X13]

  (6) 0x40138c FMLA	V20.2D, V21.2D, V30.2D

  (6) 0x401390 STR	Q20, [X17, X13]

  (6) 0x401394 LDR	Q19, [X20, X14]

  (6) 0x401398 LDR	Q18, [X18, X14]

  (6) 0x40139c FMLA	V18.2D, V19.2D, V30.2D

  (6) 0x4013a0 STR	Q18, [X17, X14]

  (6) 0x4013a4 LDR	Q17, [X20, X11]

  (6) 0x4013a8 LDR	Q16, [X18, X11]

  (6) 0x4013ac FMLA	V16.2D, V17.2D, V30.2D

  (6) 0x4013b0 STR	Q16, [X17, X11]

  (6) 0x4013b4 CMP	X30, X0

  (6) 0x4013b8 B.NE	401314

0x4013bc AND	X17, X5, #8127

0x4013c0 TBZ	W5, #0, 4013dc

0x4013c4 ADD	X1, X1, X17

0x4013c8 UBFM	X5, X1, #61, #60

0x4013cc LDR	D30, [X9, X5]

0x4013d0 LDR	D7, [X8, X5]

0x4013d4 FMADD	D31, D31, D30, D7

0x4013d8 STR	D31, [X10, X5]

0x4013dc LDP	X19, X20, [SP, #16]

0x4013e0 LDP	X29, X30, [SP], #32

0x4013e4 RET

0x4013e8 ADD	X5, X5, #1

0x4013ec MOVZ	X0, #0

0x4013f0 B	4011d4

0x4013f4 SUB	X15, X12, X1

0x4013f8 ANDS	X18, X15, #4224

0x4013fc B.EQ	4014c4

0x401400 CMP	X18, #1

0x401404 B.EQ	4014a8

0x401408 CMP	X18, #2

0x40140c B.EQ	401494

0x401410 CMP	X18, #3

0x401414 B.EQ	401480

0x401418 CMP	X18, #4

0x40141c B.EQ	40146c

0x401420 CMP	X18, #5

0x401424 B.EQ	401458

0x401428 CMP	X18, #6

0x40142c B.EQ	401444

0x401430 LDR	D6, [X9, X1,LSL #3]

0x401434 LDR	D5, [X8, X1,LSL #3]

0x401438 FMADD	D4, D31, D6, D5

0x40143c STR	D4, [X10, X1,LSL #3]

0x401440 ADD	X1, X1, #1

0x401444 LDR	D3, [X9, X1,LSL #3]

0x401448 LDR	D2, [X8, X1,LSL #3]

0x40144c FMADD	D1, D31, D3, D2

0x401450 STR	D1, [X10, X1,LSL #3]

0x401454 ADD	X1, X1, #1

0x401458 LDR	D29, [X9, X1,LSL #3]

0x40145c LDR	D0, [X8, X1,LSL #3]

0x401460 FMADD	D28, D31, D29, D0

0x401464 STR	D28, [X10, X1,LSL #3]

0x401468 ADD	X1, X1, #1

0x40146c LDR	D27, [X9, X1,LSL #3]

0x401470 LDR	D26, [X8, X1,LSL #3]

0x401474 FMADD	D25, D31, D27, D26

0x401478 STR	D25, [X10, X1,LSL #3]

0x40147c ADD	X1, X1, #1

0x401480 LDR	D24, [X9, X1,LSL #3]

0x401484 LDR	D23, [X8, X1,LSL #3]

0x401488 FMADD	D22, D31, D24, D23

0x40148c STR	D22, [X10, X1,LSL #3]

0x401490 ADD	X1, X1, #1

0x401494 LDR	D21, [X9, X1,LSL #3]

0x401498 LDR	D20, [X8, X1,LSL #3]

0x40149c FMADD	D19, D31, D21, D20

0x4014a0 STR	D19, [X10, X1,LSL #3]

0x4014a4 ADD	X1, X1, #1

0x4014a8 LDR	D18, [X9, X1,LSL #3]

0x4014ac LDR	D17, [X8, X1,LSL #3]

0x4014b0 FMADD	D16, D31, D18, D17

0x4014b4 STR	D16, [X10, X1,LSL #3]

0x4014b8 ADD	X1, X1, #1

0x4014bc CMP	X12, X1

0x4014c0 B.EQ	4013dc

  (5) 0x4014c4 LDR	D30, [X9, X1,LSL #3]

  (5) 0x4014c8 ADD	X30, X1, #1

  (5) 0x4014cc ADD	X16, X1, #2

  (5) 0x4014d0 ADD	X20, X1, #3

  (5) 0x4014d4 ADD	X19, X1, #4

  (5) 0x4014d8 LDR	D7, [X8, X1,LSL #3]

  (5) 0x4014dc ADD	X2, X1, #5

  (5) 0x4014e0 ADD	X0, X1, #6

  (5) 0x4014e4 ADD	X3, X1, #7

  (5) 0x4014e8 FMADD	D6, D31, D30, D7

  (5) 0x4014ec STR	D6, [X10, X1,LSL #3]

  (5) 0x4014f0 ADD	X1, X1, #8

  (5) 0x4014f4 LDR	D5, [X9, X30,LSL #3]

  (5) 0x4014f8 LDR	D4, [X8, X30,LSL #3]

  (5) 0x4014fc FMADD	D3, D31, D5, D4

  (5) 0x401500 STR	D3, [X10, X30,LSL #3]

  (5) 0x401504 LDR	D2, [X9, X16,LSL #3]

  (5) 0x401508 LDR	D1, [X8, X16,LSL #3]

  (5) 0x40150c FMADD	D29, D31, D2, D1

  (5) 0x401510 STR	D29, [X10, X16,LSL #3]

  (5) 0x401514 LDR	D0, [X9, X20,LSL #3]

  (5) 0x401518 LDR	D28, [X8, X20,LSL #3]

  (5) 0x40151c FMADD	D27, D31, D0, D28

  (5) 0x401520 STR	D27, [X10, X20,LSL #3]

  (5) 0x401524 LDR	D26, [X9, X19,LSL #3]

  (5) 0x401528 LDR	D25, [X8, X19,LSL #3]

  (5) 0x40152c FMADD	D24, D31, D26, D25

  (5) 0x401530 STR	D24, [X10, X19,LSL #3]

  (5) 0x401534 LDR	D23, [X9, X2,LSL #3]

  (5) 0x401538 LDR	D22, [X8, X2,LSL #3]

  (5) 0x40153c FMADD	D21, D31, D23, D22

  (5) 0x401540 STR	D21, [X10, X2,LSL #3]

  (5) 0x401544 LDR	D20, [X9, X0,LSL #3]

  (5) 0x401548 LDR	D19, [X8, X0,LSL #3]

  (5) 0x40154c FMADD	D18, D31, D20, D19

  (5) 0x401550 STR	D18, [X10, X0,LSL #3]

  (5) 0x401554 LDR	D17, [X9, X3,LSL #3]

  (5) 0x401558 LDR	D16, [X8, X3,LSL #3]

  (5) 0x40155c FMADD	D30, D31, D17, D16

  (5) 0x401560 STR	D30, [X10, X3,LSL #3]

  (5) 0x401564 CMP	X12, X1

  (5) 0x401568 B.NE	4014c4

0x40156c B	4013dc

/home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c: 358 - 360

--------------------------------------------------------------------------------

358: #pragma omp parallel for

359: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

360: 	    a[j] = b[j]+scalar*c[j];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.19
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.26
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	main._omp_fn.7
Source	stream.c:358-360
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.38
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	17.88
CQA cycles if fully vectorized	14.56
Front-end cycles	18.38
P0 cycles	11.50
P1 cycles	11.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	9.50
P6 cycles	9.50
P7 cycles	9.50
P8 cycles	7.75
P9 cycles	7.75
P10 cycles	7.75
P11 cycles	7.75
P12 cycles	17.17
P13 cycles	16.83
P14 cycles	17.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	147.00
Nb uops	147.00
Nb loads	NA
Nb stores	15.00
Nb stack references	2.00
FLOP/cycle	2.39
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	22.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.65
Bytes prefetched	0.00
Bytes loaded	424.00
Bytes stored	176.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	31.87
Vectorization ratio load	43.75
Vectorization ratio store	46.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	46.67
Vectorization ratio div_sqrt	NA
Vectorization ratio other	4.55
Vector-efficiency ratio all	66.48
Vector-efficiency ratio load	73.44
Vector-efficiency ratio store	73.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	73.33
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	52.27

Metric	Value
CQA speedup if no scalar integer	1.19
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.26
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	main._omp_fn.7
Source	stream.c:358-360
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.38
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	17.88
CQA cycles if fully vectorized	14.56
Front-end cycles	18.38
P0 cycles	11.50
P1 cycles	11.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	9.50
P6 cycles	9.50
P7 cycles	9.50
P8 cycles	7.75
P9 cycles	7.75
P10 cycles	7.75
P11 cycles	7.75
P12 cycles	17.17
P13 cycles	16.83
P14 cycles	17.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	147.00
Nb uops	147.00
Nb loads	NA
Nb stores	15.00
Nb stack references	2.00
FLOP/cycle	2.39
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	22.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.65
Bytes prefetched	0.00
Bytes loaded	424.00
Bytes stored	176.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	31.87
Vectorization ratio load	43.75
Vectorization ratio store	46.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	46.67
Vectorization ratio div_sqrt	NA
Vectorization ratio other	4.55
Vector-efficiency ratio all	66.48
Vector-efficiency ratio load	73.44
Vector-efficiency ratio store	73.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	73.33
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	52.27

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.7
Source file and lines	stream.c:358-360
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:358-360.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.38 to 15.50 cycles (1.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 66% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 18.38 to 14.56 cycles (1.26x speedup).

Details

31% of VPU instructions are used in vector version (process two or more data elements in vector registers):

43% of VPU loads are used in vector version.
46% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
46% of VPU fused multiply-add instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 22 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 44 FP arithmetical operations:

22: addition or subtraction (all inside FMA instructions)
22: multiply (all inside FMA instructions)

The binary loop is loading 424 bytes. The binary loop is storing 176 bytes.

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	147
nb uops	147
loop length	588
used w registers	1
used x registers	23
used b registers	0
used h registers	0
used s registers	1
used d registers	24
used q registers	14
used v registers	16
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.38 cycles
front end	18.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	9.50	9.50	9.50	9.50	9.50	9.50	7.75	7.75	7.75	7.75	17.17	16.83	17.00	0.00	0.00
cycles	11.50	11.50	9.50	9.50	9.50	9.50	9.50	9.50	7.75	7.75	7.75	7.75	17.17	16.83	17.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.38
Dispatch	17.17
Overall L1	18.38

Vectorization ratios

INT

all	28%
load	43%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	46%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	31%
load	43%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	46%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	65%
load	73%
store	73%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	52%

all	73%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	73%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	66%
load	73%
store	73%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	73%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	52%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.38 cycles. At this rate:

24% of peak load performance is reached (23.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.58 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.38 to 17.17 cycles (1.07x speedup).

ASM code

In the binary file, the address of the loop is: 4013e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MADD X1, X5, X1, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X12, X5, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X1, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4013dc <main._omp_fn.7+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, 4011e4 <main._omp_fn.7+0x44>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR X6, [X3, #1392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X8, X9, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4013f4 <main._omp_fn.7+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X11, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X17, X10, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X8, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X9, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X13, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X14, X17, #4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.EQ 4013f4 <main._omp_fn.7+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X15, X5, #1, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP V30.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD X18, X8, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X30, X15, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X16, X30, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X20, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X19, X16, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X2, X19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X12, X2, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401314 <main._omp_fn.7+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4012f8 <main._omp_fn.7+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4012e4 <main._omp_fn.7+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4012d0 <main._omp_fn.7+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4012bc <main._omp_fn.7+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4012a8 <main._omp_fn.7+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401294 <main._omp_fn.7+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q23, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVZ X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q22, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V22.2D, V23.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q22, [X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q21, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q20, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V20.2D, V21.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q20, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q19, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q18, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V18.2D, V19.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q18, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q17, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q16, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V16.2D, V17.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q16, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q7, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q6, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V6.2D, V7.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q6, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q5, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q4, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V4.2D, V5.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q4, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q3, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q2, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V2.2D, V3.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q2, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X30, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4013bc <main._omp_fn.7+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X17, X5, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W5, #0, 4013dc <main._omp_fn.7+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X5, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D30, [X9, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D7, [X8, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D31, D30, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D31, [X10, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 4011d4 <main._omp_fn.7+0x34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X15, X12, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X18, X15, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4014c4 <main._omp_fn.7+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4014a8 <main._omp_fn.7+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401494 <main._omp_fn.7+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401480 <main._omp_fn.7+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40146c <main._omp_fn.7+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401458 <main._omp_fn.7+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401444 <main._omp_fn.7+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D5, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D4, D31, D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D4, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D3, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D1, D31, D3, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D1, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D29, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D0, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D28, D31, D29, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D28, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D27, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D26, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D25, D31, D27, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D25, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D24, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D23, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D22, D31, D24, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D22, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D21, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D20, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D19, D31, D21, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D19, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D18, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D17, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D16, D31, D18, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D16, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X12, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4013dc <main._omp_fn.7+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4013dc <main._omp_fn.7+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.7
Source file and lines	stream.c:358-360
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:358-360.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

31% of VPU instructions are used in vector version (process two or more data elements in vector registers):

43% of VPU loads are used in vector version.
46% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
46% of VPU fused multiply-add instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 22 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 44 FP arithmetical operations:

22: addition or subtraction (all inside FMA instructions)
22: multiply (all inside FMA instructions)

The binary loop is loading 424 bytes. The binary loop is storing 176 bytes.

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	147
nb uops	147
loop length	588
used w registers	1
used x registers	23
used b registers	0
used h registers	0
used s registers	1
used d registers	24
used q registers	14
used v registers	16
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.38 cycles
front end	18.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	9.50	9.50	9.50	9.50	9.50	9.50	7.75	7.75	7.75	7.75	17.17	16.83	17.00	0.00	0.00
cycles	11.50	11.50	9.50	9.50	9.50	9.50	9.50	9.50	7.75	7.75	7.75	7.75	17.17	16.83	17.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.38
Dispatch	17.17
Overall L1	18.38

Vectorization ratios

INT

all	28%
load	43%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	46%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	31%
load	43%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	46%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	65%
load	73%
store	73%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	52%

all	73%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	73%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	66%
load	73%
store	73%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	73%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	52%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.38 cycles. At this rate:

24% of peak load performance is reached (23.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.58 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4013e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
MADD X1, X5, X1, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X12, X5, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X1, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4013dc <main._omp_fn.7+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, 4011e4 <main._omp_fn.7+0x44>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR X6, [X3, #1392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X8, X9, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4013f4 <main._omp_fn.7+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X11, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X17, X10, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X8, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X9, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X13, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X14, X17, #4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.EQ 4013f4 <main._omp_fn.7+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X15, X5, #1, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP V30.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD X18, X8, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X30, X15, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X16, X30, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X20, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X19, X16, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X2, X19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X12, X2, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401314 <main._omp_fn.7+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4012f8 <main._omp_fn.7+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4012e4 <main._omp_fn.7+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4012d0 <main._omp_fn.7+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4012bc <main._omp_fn.7+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4012a8 <main._omp_fn.7+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401294 <main._omp_fn.7+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q23, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVZ X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q22, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V22.2D, V23.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q22, [X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q21, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q20, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V20.2D, V21.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q20, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q19, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q18, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V18.2D, V19.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q18, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q17, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q16, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V16.2D, V17.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q16, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q7, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q6, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V6.2D, V7.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q6, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q5, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q4, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V4.2D, V5.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q4, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q3, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q2, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V2.2D, V3.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q2, [X17, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X30, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4013bc <main._omp_fn.7+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X17, X5, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W5, #0, 4013dc <main._omp_fn.7+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X5, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D30, [X9, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D7, [X8, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D31, D31, D30, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D31, [X10, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 4011d4 <main._omp_fn.7+0x34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X15, X12, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X18, X15, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4014c4 <main._omp_fn.7+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4014a8 <main._omp_fn.7+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401494 <main._omp_fn.7+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401480 <main._omp_fn.7+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40146c <main._omp_fn.7+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401458 <main._omp_fn.7+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401444 <main._omp_fn.7+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D5, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D4, D31, D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D4, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D3, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D1, D31, D3, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D1, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D29, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D0, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D28, D31, D29, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D28, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D27, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D26, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D25, D31, D27, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D25, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D24, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D23, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D22, D31, D24, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D22, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D21, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D20, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D19, D31, D21, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D19, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D18, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D17, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D16, D31, D18, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D16, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X12, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 4013dc <main._omp_fn.7+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4013dc <main._omp_fn.7+0x23c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code