OV - exec - Loop 15

	Loop Id: 15	Module: exec	Source: stream.c:324-324	Coverage: 19.34%

0x401ee8 LDR	Q21, [X18, X1]    [3]

0x401eec ADD	X7, X1, #32

0x401ef0 ADD	X15, X1, #64

0x401ef4 ADD	X10, X1, #96

0x401ef8 ADD	X14, X1, #128

0x401efc LDR	Q20, [X19, X1]    [4]

0x401f00 ADD	X13, X1, #160

0x401f04 ADD	X12, X1, #192

0x401f08 ADD	X11, X1, #224

0x401f0c STR	Q21, [X17, X1]    [1]

0x401f10 STR	Q20, [X2, X1]    [2]

0x401f14 ADD	X1, X1, #256

0x401f18 LDR	Q23, [X18, X7]    [3]

0x401f1c LDR	Q22, [X19, X7]    [4]

0x401f20 STR	Q23, [X17, X7]    [1]

0x401f24 STR	Q22, [X2, X7]    [2]

0x401f28 LDR	Q25, [X18, X15]    [3]

0x401f2c LDR	Q24, [X19, X15]    [4]

0x401f30 STR	Q25, [X17, X15]    [1]

0x401f34 STR	Q24, [X2, X15]    [2]

0x401f38 LDR	Q27, [X18, X10]    [3]

0x401f3c LDR	Q26, [X19, X10]    [4]

0x401f40 STR	Q27, [X17, X10]    [1]

0x401f44 STR	Q26, [X2, X10]    [2]

0x401f48 LDR	Q29, [X18, X14]    [3]

0x401f4c LDR	Q28, [X19, X14]    [4]

0x401f50 STR	Q29, [X17, X14]    [1]

0x401f54 STR	Q28, [X2, X14]    [2]

0x401f58 LDR	Q30, [X18, X13]    [3]

0x401f5c LDR	Q31, [X19, X13]    [4]

0x401f60 STR	Q30, [X17, X13]    [1]

0x401f64 STR	Q31, [X2, X13]    [2]

0x401f68 LDR	Q1, [X18, X12]    [3]

0x401f6c LDR	Q0, [X19, X12]    [4]

0x401f70 STR	Q1, [X17, X12]    [1]

0x401f74 STR	Q0, [X2, X12]    [2]

0x401f78 LDR	Q3, [X18, X11]    [3]

0x401f7c LDR	Q2, [X19, X11]    [4]

0x401f80 STR	Q3, [X17, X11]    [1]

0x401f84 STR	Q2, [X2, X11]    [2]

0x401f88 CMP	X1, X30

0x401f8c B.NE	401ee8

/home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c: 324 - 324

--------------------------------------------------------------------------------

324: 	    c[j] = a[j];

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.04+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	main	stream.c:327	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	stream.c:290	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P12, P13, P14,
Function	main._omp_fn.4
Source	stream.c:324-324
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	10.67
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	10.67
Front-end cycles	5.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.58
P3 cycles	1.58
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	1.42
P7 cycles	1.42
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	10.67
P13 cycles	10.67
P14 cycles	10.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P12, P13, P14,
Function	main._omp_fn.4
Source	stream.c:324-324
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	10.67
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	10.67
Front-end cycles	5.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.58
P3 cycles	1.58
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	1.42
P7 cycles	1.42
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	10.67
P13 cycles	10.67
P14 cycles	10.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.4
Source file and lines	stream.c:324-324
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:324.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	42
nb uops	42
loop length	168
used w registers	0
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	16
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00
cycles	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

24% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
49% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401ee8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR Q21, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X7, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X15, X1, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X10, X1, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X14, X1, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q20, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X13, X1, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X12, X1, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X11, X1, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR Q21, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q20, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q23, [X18, X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q22, [X19, X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q23, [X17, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q22, [X2, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q25, [X18, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q24, [X19, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q25, [X17, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q24, [X2, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q27, [X18, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q26, [X19, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q27, [X17, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q26, [X2, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q29, [X18, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q28, [X19, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q29, [X17, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q28, [X2, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q30, [X18, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q31, [X19, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q30, [X17, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q31, [X2, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q1, [X18, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q0, [X19, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q1, [X17, X12]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q0, [X2, X12]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q3, [X18, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q2, [X19, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q3, [X17, X11]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q2, [X2, X11]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
CMP X1, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 401ee8 <main._omp_fn.4+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.4
Source file and lines	stream.c:324-324
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:324.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	42
nb uops	42
loop length	168
used w registers	0
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	16
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00
cycles	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

24% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
49% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401ee8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR Q21, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X7, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X15, X1, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X10, X1, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X14, X1, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q20, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X13, X1, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X12, X1, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X11, X1, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR Q21, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q20, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q23, [X18, X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q22, [X19, X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q23, [X17, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q22, [X2, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q25, [X18, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q24, [X19, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q25, [X17, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q24, [X2, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q27, [X18, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q26, [X19, X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q27, [X17, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q26, [X2, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q29, [X18, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q28, [X19, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q29, [X17, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q28, [X2, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q30, [X18, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q31, [X19, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q30, [X17, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q31, [X2, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q1, [X18, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q0, [X19, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q1, [X17, X12]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q0, [X2, X12]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q3, [X18, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q2, [X19, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q3, [X17, X11]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q2, [X2, X11]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
CMP X1, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 401ee8 <main._omp_fn.4+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code