OV - exec - Loop 13

	Loop Id: 13	Module: exec	Source: stream.c:322-324	Coverage: 0.00%

0x401dc0 MADD	X0, X4, X0, X2

0x401dc4 ADD	X5, X4, X0

0x401dc8 CMP	X0, X5

0x401dcc B.GE	401fc4

0x401dd0 ADRP	X3, 402dd0

0x401dd4 LDR	X6, [X3, #280]

0x401dd8 LDP	X8, X9, [X6, #8]

0x401ddc CMP	X4, #1

0x401de0 B.EQ	401ff0

0x401de4 UBFM	X7, X0, #61, #60

0x401de8 ADD	X17, X8, X0,LSL #3

0x401dec ADD	X10, X7, #8

0x401df0 ADD	X11, X9, X10

0x401df4 SUB	X12, X17, X11

0x401df8 CMP	X12, #16

0x401dfc B.LS	401ff0

0x401e00 SUB	X13, X4, #1

0x401e04 CMP	X13, #2

0x401e08 B.LS	40210c

0x401e0c UBFM	X15, X4, #2, #63

0x401e10 ADD	X18, X9, X7

0x401e14 UBFM	X30, X15, #59, #58

0x401e18 MOVZ	X1, #0

0x401e1c SUB	X16, X30, #32

0x401e20 ADD	X19, X18, #16

0x401e24 UBFM	X5, X16, #5, #63

0x401e28 ADD	X2, X17, #16

0x401e2c ADD	X3, X5, #1

0x401e30 ANDS	X6, X3, #4224

0x401e34 B.EQ	401ee8

0x401e38 CMP	X6, #1

0x401e3c B.EQ	401ecc

0x401e40 CMP	X6, #2

0x401e44 B.EQ	401eb8

0x401e48 CMP	X6, #3

0x401e4c B.EQ	401ea4

0x401e50 CMP	X6, #4

0x401e54 B.EQ	401e90

0x401e58 CMP	X6, #5

0x401e5c B.EQ	401e7c

0x401e60 CMP	X6, #6

0x401e64 B.NE	4020f4

0x401e68 LDR	Q1, [X18, X1]

0x401e6c LDR	Q0, [X19, X1]

0x401e70 STR	Q1, [X17, X1]

0x401e74 STR	Q0, [X2, X1]

0x401e78 ADD	X1, X1, #32

0x401e7c LDR	Q3, [X18, X1]

0x401e80 LDR	Q2, [X19, X1]

0x401e84 STR	Q3, [X17, X1]

0x401e88 STR	Q2, [X2, X1]

0x401e8c ADD	X1, X1, #32

0x401e90 LDR	Q5, [X18, X1]

0x401e94 LDR	Q4, [X19, X1]

0x401e98 STR	Q5, [X17, X1]

0x401e9c STR	Q4, [X2, X1]

0x401ea0 ADD	X1, X1, #32

0x401ea4 LDR	Q7, [X18, X1]

0x401ea8 LDR	Q6, [X19, X1]

0x401eac STR	Q7, [X17, X1]

0x401eb0 STR	Q6, [X2, X1]

0x401eb4 ADD	X1, X1, #32

0x401eb8 LDR	Q17, [X18, X1]

0x401ebc LDR	Q16, [X19, X1]

0x401ec0 STR	Q17, [X17, X1]

0x401ec4 STR	Q16, [X2, X1]

0x401ec8 ADD	X1, X1, #32

0x401ecc LDR	Q19, [X18, X1]

0x401ed0 LDR	Q18, [X19, X1]

0x401ed4 STR	Q19, [X17, X1]

0x401ed8 STR	Q18, [X2, X1]

0x401edc ADD	X1, X1, #32

0x401ee0 CMP	X1, X30

0x401ee4 B.EQ	401f90

  (15) 0x401ee8 LDR	Q21, [X18, X1]

  (15) 0x401eec ADD	X7, X1, #32

  (15) 0x401ef0 ADD	X15, X1, #64

  (15) 0x401ef4 ADD	X10, X1, #96

  (15) 0x401ef8 ADD	X14, X1, #128

  (15) 0x401efc LDR	Q20, [X19, X1]

  (15) 0x401f00 ADD	X13, X1, #160

  (15) 0x401f04 ADD	X12, X1, #192

  (15) 0x401f08 ADD	X11, X1, #224

  (15) 0x401f0c STR	Q21, [X17, X1]

  (15) 0x401f10 STR	Q20, [X2, X1]

  (15) 0x401f14 ADD	X1, X1, #256

  (15) 0x401f18 LDR	Q23, [X18, X7]

  (15) 0x401f1c LDR	Q22, [X19, X7]

  (15) 0x401f20 STR	Q23, [X17, X7]

  (15) 0x401f24 STR	Q22, [X2, X7]

  (15) 0x401f28 LDR	Q25, [X18, X15]

  (15) 0x401f2c LDR	Q24, [X19, X15]

  (15) 0x401f30 STR	Q25, [X17, X15]

  (15) 0x401f34 STR	Q24, [X2, X15]

  (15) 0x401f38 LDR	Q27, [X18, X10]

  (15) 0x401f3c LDR	Q26, [X19, X10]

  (15) 0x401f40 STR	Q27, [X17, X10]

  (15) 0x401f44 STR	Q26, [X2, X10]

  (15) 0x401f48 LDR	Q29, [X18, X14]

  (15) 0x401f4c LDR	Q28, [X19, X14]

  (15) 0x401f50 STR	Q29, [X17, X14]

  (15) 0x401f54 STR	Q28, [X2, X14]

  (15) 0x401f58 LDR	Q30, [X18, X13]

  (15) 0x401f5c LDR	Q31, [X19, X13]

  (15) 0x401f60 STR	Q30, [X17, X13]

  (15) 0x401f64 STR	Q31, [X2, X13]

  (15) 0x401f68 LDR	Q1, [X18, X12]

  (15) 0x401f6c LDR	Q0, [X19, X12]

  (15) 0x401f70 STR	Q1, [X17, X12]

  (15) 0x401f74 STR	Q0, [X2, X12]

  (15) 0x401f78 LDR	Q3, [X18, X11]

  (15) 0x401f7c LDR	Q2, [X19, X11]

  (15) 0x401f80 STR	Q3, [X17, X11]

  (15) 0x401f84 STR	Q2, [X2, X11]

  (15) 0x401f88 CMP	X1, X30

  (15) 0x401f8c B.NE	401ee8

0x401f90 AND	X14, X4, #8062

0x401f94 CMP	X4, X14

0x401f98 B.EQ	401fc4

0x401f9c ADD	X0, X0, X14

0x401fa0 SUB	X4, X4, X14

0x401fa4 WHILELO	P7.D, XZR, X4

0x401fa8 LD1D	{Z4.D}, P7/Z, [X9, X0,LSL #3]

0x401fac ADD	X8, X8, X0,LSL #3

0x401fb0 ST1D	{Z4.D}, P7, [X8, MUL VL]

0x401fb4 CNTD	X17, ALL

0x401fb8 WHILELO	P0.D, X17, X4

0x401fbc ADD	X9, X9, X0,LSL #3

0x401fc0 B.NE	401fdc

0x401fc4 LDR	X19, [SP, #16]

0x401fc8 LDP	X29, X30, [SP], #32

0x401fcc RET

0x401fd0 ADD	X4, X4, #1

0x401fd4 MOVZ	X2, #0

0x401fd8 B	401dc0

0x401fdc LDR	X19, [SP, #16]

0x401fe0 LD1D	{Z5.D}, P0/Z, [X9, #1, MUL VL]

0x401fe4 ST1D	{Z5.D}, P0, [X8, #1, MUL VL]

0x401fe8 LDP	X29, X30, [SP], #32

0x401fec RET

0x401ff0 SUB	X18, X5, X0

0x401ff4 ANDS	X30, X18, #4224

0x401ff8 B.EQ	402088

0x401ffc CMP	X30, #1

0x402000 B.EQ	402074

0x402004 CMP	X30, #2

0x402008 B.EQ	402068

0x40200c CMP	X30, #3

0x402010 B.EQ	40205c

0x402014 CMP	X30, #4

0x402018 B.EQ	402050

0x40201c CMP	X30, #5

0x402020 B.EQ	402044

0x402024 CMP	X30, #6

0x402028 B.EQ	402038

0x40202c LDR	D6, [X9, X0,LSL #3]

0x402030 STR	D6, [X8, X0,LSL #3]

0x402034 ADD	X0, X0, #1

0x402038 LDR	D7, [X9, X0,LSL #3]

0x40203c STR	D7, [X8, X0,LSL #3]

0x402040 ADD	X0, X0, #1

0x402044 LDR	D16, [X9, X0,LSL #3]

0x402048 STR	D16, [X8, X0,LSL #3]

0x40204c ADD	X0, X0, #1

0x402050 LDR	D17, [X9, X0,LSL #3]

0x402054 STR	D17, [X8, X0,LSL #3]

0x402058 ADD	X0, X0, #1

0x40205c LDR	D18, [X9, X0,LSL #3]

0x402060 STR	D18, [X8, X0,LSL #3]

0x402064 ADD	X0, X0, #1

0x402068 LDR	D19, [X9, X0,LSL #3]

0x40206c STR	D19, [X8, X0,LSL #3]

0x402070 ADD	X0, X0, #1

0x402074 LDR	D20, [X9, X0,LSL #3]

0x402078 STR	D20, [X8, X0,LSL #3]

0x40207c ADD	X0, X0, #1

0x402080 CMP	X5, X0

0x402084 B.EQ	401fc4

  (14) 0x402088 LDR	D21, [X9, X0,LSL #3]

  (14) 0x40208c ADD	X19, X0, #1

  (14) 0x402090 ADD	X1, X0, #2

  (14) 0x402094 ADD	X16, X0, #3

  (14) 0x402098 ADD	X6, X0, #4

  (14) 0x40209c ADD	X7, X0, #5

  (14) 0x4020a0 ADD	X3, X0, #6

  (14) 0x4020a4 ADD	X2, X0, #7

  (14) 0x4020a8 STR	D21, [X8, X0,LSL #3]

  (14) 0x4020ac ADD	X0, X0, #8

  (14) 0x4020b0 LDR	D22, [X9, X19,LSL #3]

  (14) 0x4020b4 STR	D22, [X8, X19,LSL #3]

  (14) 0x4020b8 LDR	D23, [X9, X1,LSL #3]

  (14) 0x4020bc STR	D23, [X8, X1,LSL #3]

  (14) 0x4020c0 LDR	D24, [X9, X16,LSL #3]

  (14) 0x4020c4 STR	D24, [X8, X16,LSL #3]

  (14) 0x4020c8 LDR	D25, [X9, X6,LSL #3]

  (14) 0x4020cc STR	D25, [X8, X6,LSL #3]

  (14) 0x4020d0 LDR	D26, [X9, X7,LSL #3]

  (14) 0x4020d4 STR	D26, [X8, X7,LSL #3]

  (14) 0x4020d8 LDR	D27, [X9, X3,LSL #3]

  (14) 0x4020dc STR	D27, [X8, X3,LSL #3]

  (14) 0x4020e0 LDR	D28, [X9, X2,LSL #3]

  (14) 0x4020e4 STR	D28, [X8, X2,LSL #3]

  (14) 0x4020e8 CMP	X5, X0

  (14) 0x4020ec B.NE	402088

0x4020f0 B	401fc4

0x4020f4 LDR	Q30, [X18]

0x4020f8 MOVZ	X1, #32

0x4020fc LDR	Q31, [X19]

0x402100 STR	Q30, [X17]

0x402104 STR	Q31, [X2]

0x402108 B	401e68

0x40210c MOVZ	X14, #0

0x402110 B	401f9c

/home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c: 322 - 324

--------------------------------------------------------------------------------

322: #pragma omp parallel for

323: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

324: 	    c[j] = a[j];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.17
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	main._omp_fn.4
Source	stream.c:322-324
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.13
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	18.13
CQA cycles if fully vectorized	15.38
Front-end cycles	18.13
P0 cycles	14.00
P1 cycles	14.00
P2 cycles	10.83
P3 cycles	10.83
P4 cycles	10.83
P5 cycles	10.83
P6 cycles	10.83
P7 cycles	10.83
P8 cycles	11.50
P9 cycles	11.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	17.50
P13 cycles	17.17
P14 cycles	17.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	145.00
Nb uops	145.00
Nb loads	NA
Nb stores	23.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.40
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	312.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.51
Vectorization ratio load	64.00
Vectorization ratio store	69.57
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	71.52
Vector-efficiency ratio load	86.00
Vector-efficiency ratio store	84.78
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.17
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	main._omp_fn.4
Source	stream.c:322-324
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.13
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	18.13
CQA cycles if fully vectorized	15.38
Front-end cycles	18.13
P0 cycles	14.00
P1 cycles	14.00
P2 cycles	10.83
P3 cycles	10.83
P4 cycles	10.83
P5 cycles	10.83
P6 cycles	10.83
P7 cycles	10.83
P8 cycles	11.50
P9 cycles	11.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	17.50
P13 cycles	17.17
P14 cycles	17.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	145.00
Nb uops	145.00
Nb loads	NA
Nb stores	23.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.40
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	312.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.51
Vectorization ratio load	64.00
Vectorization ratio store	69.57
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	71.52
Vector-efficiency ratio load	86.00
Vector-efficiency ratio store	84.78
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.4
Source file and lines	stream.c:322-324
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:322-324.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.13 to 15.50 cycles (1.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 71% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 18.13 to 15.37 cycles (1.18x speedup).

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

64% of VPU loads are used in vector version.
69% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 384 bytes. The binary loop is storing 312 bytes.

General properties

nb instructions	145
nb uops	145
loop length	580
used w registers	0
used x registers	23
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	14
used v registers	0
used z registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.13 cycles
front end	18.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	14.00	14.00	10.83	10.83	10.83	10.83	10.83	10.83	11.50	11.50	0.00	0.00	17.50	17.17	17.33	0.00	0.00
cycles	14.00	14.00	10.83	10.83	10.83	10.83	10.83	10.83	11.50	11.50	0.00	0.00	17.50	17.17	17.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.13
Dispatch	17.50
Overall L1	18.13

Vectorization ratios

all	40%
load	64%
store	69%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	71%
load	86%
store	84%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.13 cycles. At this rate:

22% of peak load performance is reached (21.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (17.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 401fd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
MADD X0, X4, X0, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X5, X4, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X0, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 401fc4 <main._omp_fn.4+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, 402dd0 <checkSTREAMresults+0x5d0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X6, [X3, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X8, X9, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401ff0 <main._omp_fn.4+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X7, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X17, X8, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X10, X7, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X12, X17, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X12, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 401ff0 <main._omp_fn.4+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X13, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 40210c <main._omp_fn.4+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X15, X4, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X9, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM X30, X15, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X16, X30, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X19, X18, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM X5, X16, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X2, X17, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X3, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ANDS X6, X3, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 401ee8 <main._omp_fn.4+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401ecc <main._omp_fn.4+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401eb8 <main._omp_fn.4+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401ea4 <main._omp_fn.4+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401e90 <main._omp_fn.4+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401e7c <main._omp_fn.4+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4020f4 <main._omp_fn.4+0x364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q1, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q0, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q1, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q0, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q3, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q2, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q3, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q2, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q5, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q4, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q5, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q4, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q7, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q6, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q7, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q6, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q17, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q16, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q17, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q16, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q19, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q18, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q19, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q18, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X1, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401f90 <main._omp_fn.4+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X14, X4, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X4, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401fc4 <main._omp_fn.4+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X4, X4, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
WHILELO P7.D, XZR, X4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	1	N/A
LD1D {Z4.D}, P7/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X8, X8, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ST1D {Z4.D}, P7, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
CNTD X17, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
WHILELO P0.D, X17, X4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	1	N/A
ADD X9, X9, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B.NE 401fdc <main._omp_fn.4+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 401dc0 <main._omp_fn.4+0x30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LD1D {Z5.D}, P0/Z, [X9, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ST1D {Z5.D}, P0, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X18, X5, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ANDS X30, X18, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402088 <main._omp_fn.4+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402074 <main._omp_fn.4+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402068 <main._omp_fn.4+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40205c <main._omp_fn.4+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402050 <main._omp_fn.4+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402044 <main._omp_fn.4+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402038 <main._omp_fn.4+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D6, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D7, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D7, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D16, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D16, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D17, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D17, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D18, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D18, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D19, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D19, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D20, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D20, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X5, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 401fc4 <main._omp_fn.4+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 401fc4 <main._omp_fn.4+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVZ X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q31, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q30, [X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q31, [X2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
B 401e68 <main._omp_fn.4+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X14, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
B 401f9c <main._omp_fn.4+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.4
Source file and lines	stream.c:322-324
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:322-324.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

64% of VPU loads are used in vector version.
69% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 384 bytes. The binary loop is storing 312 bytes.

General properties

nb instructions	145
nb uops	145
loop length	580
used w registers	0
used x registers	23
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	14
used v registers	0
used z registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.13 cycles
front end	18.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	14.00	14.00	10.83	10.83	10.83	10.83	10.83	10.83	11.50	11.50	0.00	0.00	17.50	17.17	17.33	0.00	0.00
cycles	14.00	14.00	10.83	10.83	10.83	10.83	10.83	10.83	11.50	11.50	0.00	0.00	17.50	17.17	17.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.13
Dispatch	17.50
Overall L1	18.13

Vectorization ratios

all	40%
load	64%
store	69%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	71%
load	86%
store	84%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.13 cycles. At this rate:

22% of peak load performance is reached (21.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (17.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 401fd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
MADD X0, X4, X0, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X5, X4, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X0, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 401fc4 <main._omp_fn.4+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, 402dd0 <checkSTREAMresults+0x5d0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X6, [X3, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X8, X9, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401ff0 <main._omp_fn.4+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X7, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X17, X8, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X10, X7, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X12, X17, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X12, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 401ff0 <main._omp_fn.4+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X13, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 40210c <main._omp_fn.4+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X15, X4, #2, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X9, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM X30, X15, #59, #58	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X16, X30, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X19, X18, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM X5, X16, #5, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X2, X17, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X3, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ANDS X6, X3, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 401ee8 <main._omp_fn.4+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401ecc <main._omp_fn.4+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401eb8 <main._omp_fn.4+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401ea4 <main._omp_fn.4+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401e90 <main._omp_fn.4+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401e7c <main._omp_fn.4+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4020f4 <main._omp_fn.4+0x364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q1, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q0, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q1, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q0, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q3, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q2, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q3, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q2, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q5, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q4, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q5, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q4, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q7, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q6, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q7, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q6, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q17, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q16, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q17, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q16, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q19, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q18, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q19, [X17, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q18, [X2, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X1, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401f90 <main._omp_fn.4+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X14, X4, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X4, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401fc4 <main._omp_fn.4+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X4, X4, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
WHILELO P7.D, XZR, X4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	1	N/A
LD1D {Z4.D}, P7/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X8, X8, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ST1D {Z4.D}, P7, [X8, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
CNTD X17, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
WHILELO P0.D, X17, X4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	1	N/A
ADD X9, X9, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B.NE 401fdc <main._omp_fn.4+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 401dc0 <main._omp_fn.4+0x30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LD1D {Z5.D}, P0/Z, [X9, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ST1D {Z5.D}, P0, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X18, X5, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ANDS X30, X18, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402088 <main._omp_fn.4+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402074 <main._omp_fn.4+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402068 <main._omp_fn.4+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40205c <main._omp_fn.4+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402050 <main._omp_fn.4+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402044 <main._omp_fn.4+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402038 <main._omp_fn.4+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D6, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D7, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D7, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D16, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D16, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D17, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D17, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D18, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D18, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D19, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D19, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR D20, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR D20, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X5, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 401fc4 <main._omp_fn.4+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 401fc4 <main._omp_fn.4+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVZ X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q31, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q30, [X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
STR Q31, [X2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
B 401e68 <main._omp_fn.4+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X14, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
B 401f9c <main._omp_fn.4+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code