OV - exec - Loop 15

	Loop Id: 15	Module: exec	Source: stream.c:484-487	Coverage: 0.06%

0x401c60 LD1B	{Z5.B}, P0/Z, [X8, X11]    [1]

0x401c64 ADD	X14, X8, X11

0x401c68 DECW	X13, ALL

0x401c6c LD1D	{Z6.D}, P3/Z, [X14, #1, MUL VL]    [6]

0x401c70 ADD	X14, X9, X11

0x401c74 FSUB	Z5.D, Z5.D, Z2.D

0x401c78 FSUB	Z6.D, Z6.D, Z2.D

0x401c7c FCMGE	P1.D, P3/Z, Z5.D, #0

0x401c80 MOVPRFX	Z7, Z5

0x401c84 FNEG	Z7.D, P3/M, Z5.D

0x401c88 FCMGE	P2.D, P3/Z, Z6.D, #0

0x401c8c MOVPRFX	Z16, Z6

0x401c90 FNEG	Z16.D, P3/M, Z6.D

0x401c94 EOR	P1.B, P3/Z, P1.B, P3.B

0x401c98 SEL	Z5.D, P1, Z7.D, Z5.D

0x401c9c LD1B	{Z7.B}, P0/Z, [X9, X11]    [2]

0x401ca0 EOR	P2.B, P3/Z, P2.B, P3.B

0x401ca4 SEL	Z6.D, P2, Z16.D, Z6.D

0x401ca8 LD1D	{Z16.D}, P3/Z, [X14, #1, MUL VL]    [5]

0x401cac ADD	X14, X10, X11

0x401cb0 FADDA	D0, P3, D0, Z5.D

0x401cb4 FSUB	Z7.D, Z7.D, Z3.D

0x401cb8 FADDA	D0, P3, D0, Z6.D

0x401cbc FSUB	Z16.D, Z16.D, Z3.D

0x401cc0 FCMGE	P1.D, P3/Z, Z7.D, #0

0x401cc4 MOVPRFX	Z17, Z7

0x401cc8 FNEG	Z17.D, P3/M, Z7.D

0x401ccc FCMGE	P2.D, P3/Z, Z16.D, #0

0x401cd0 MOVPRFX	Z18, Z16

0x401cd4 FNEG	Z18.D, P3/M, Z16.D

0x401cd8 EOR	P1.B, P3/Z, P1.B, P3.B

0x401cdc SEL	Z7.D, P1, Z17.D, Z7.D

0x401ce0 LD1B	{Z17.B}, P0/Z, [X10, X11]    [3]

0x401ce4 EOR	P2.B, P3/Z, P2.B, P3.B

0x401ce8 ADDVL	X11, X11, #2

0x401cec SEL	Z16.D, P2, Z18.D, Z16.D

0x401cf0 LD1D	{Z18.D}, P3/Z, [X14, #1, MUL VL]    [4]

0x401cf4 FADDA	D1, P3, D1, Z7.D

0x401cf8 FSUB	Z17.D, Z17.D, Z4.D

0x401cfc FADDA	D1, P3, D1, Z16.D

0x401d00 FSUB	Z18.D, Z18.D, Z4.D

0x401d04 FCMGE	P1.D, P3/Z, Z17.D, #0

0x401d08 MOVPRFX	Z19, Z17

0x401d0c FNEG	Z19.D, P3/M, Z17.D

0x401d10 FCMGE	P2.D, P3/Z, Z18.D, #0

0x401d14 MOVPRFX	Z20, Z18

0x401d18 FNEG	Z20.D, P3/M, Z18.D

0x401d1c EOR	P1.B, P3/Z, P1.B, P3.B

0x401d20 SEL	Z17.D, P1, Z19.D, Z17.D

0x401d24 EOR	P2.B, P3/Z, P2.B, P3.B

0x401d28 SEL	Z18.D, P2, Z20.D, Z18.D

0x401d2c FADDA	D24, P3, D24, Z17.D

0x401d30 FADDA	D24, P3, D24, Z18.D

0x401d34 CBNZ	X13, 401c60

/home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c: 484 - 487

--------------------------------------------------------------------------------

484: 	for (j=0; j<STREAM_ARRAY_SIZE; j++) {

485: 		aSumErr += abs(a[j] - aj);

486: 		bSumErr += abs(b[j] - bj);

487: 		cSumErr += abs(c[j] - cj);

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:394	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P8, P9, P10, P11,
Function	checkSTREAMresults
Source	stream.c:484-487
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	9.00
Front-end cycles	6.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	6.00
P7 cycles	2.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	9.00
P11 cycles	9.00
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	2.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.00
Nb uops	54.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.67
Nb FLOP add-sub	24.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	85.71
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	92.31
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	80.00
Vector-efficiency ratio all	88.27
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	96.15
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	82.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P8, P9, P10, P11,
Function	checkSTREAMresults
Source	stream.c:484-487
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	9.00
Front-end cycles	6.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	6.00
P7 cycles	2.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	9.00
P11 cycles	9.00
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	2.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.00
Nb uops	54.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.67
Nb FLOP add-sub	24.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	85.71
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	92.31
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	80.00
Vector-efficiency ratio all	88.27
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	96.15
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	82.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	checkSTREAMresults
Source file and lines	stream.c:484-487
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:484-487.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions).

Details

85% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU addition or subtraction instructions are used in vector version.
80% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

24: addition or subtraction

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	54
nb uops	54
loop length	216
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	3
used q registers	0
used v registers	0
used z registers	11
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.75 cycles
front end	6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.83	0.83	0.67	0.67	6.00	2.00	9.00	9.00	9.00	9.00	2.00	2.00	2.00	0.00	0.00
cycles	0.50	0.50	0.83	0.83	0.67	0.67	6.00	2.00	9.00	9.00	9.00	9.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	6.75
Dispatch	9.00
Data deps.	8.00
Overall L1	9.00

Vectorization ratios

INT

all	72%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	85%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	92%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

Vector efficiency ratios

INT

all	77%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	70%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	88%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	96%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	82%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LD1B {Z5.B}, P0/Z, [X8, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X14, X8, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DECW X13, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LD1D {Z6.D}, P3/Z, [X14, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X14, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FSUB Z5.D, Z5.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB Z6.D, Z6.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P1.D, P3/Z, Z5.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z7, Z5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z7.D, P3/M, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P2.D, P3/Z, Z6.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z16, Z6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z16.D, P3/M, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P1.B, P3/Z, P1.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z5.D, P1, Z7.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1B {Z7.B}, P0/Z, [X9, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
EOR P2.B, P3/Z, P2.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z6.D, P2, Z16.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z16.D}, P3/Z, [X14, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X14, X10, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADDA D0, P3, D0, Z5.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
FSUB Z7.D, Z7.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDA D0, P3, D0, Z6.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
FSUB Z16.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P1.D, P3/Z, Z7.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z17, Z7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z17.D, P3/M, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P2.D, P3/Z, Z16.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z18.D, P3/M, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P1.B, P3/Z, P1.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z7.D, P1, Z17.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1B {Z17.B}, P0/Z, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
EOR P2.B, P3/Z, P2.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADDVL X11, X11, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
SEL Z16.D, P2, Z18.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z18.D}, P3/Z, [X14, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADDA D1, P3, D1, Z7.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
FSUB Z17.D, Z17.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDA D1, P3, D1, Z16.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
FSUB Z18.D, Z18.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P1.D, P3/Z, Z17.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z19.D, P3/M, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P2.D, P3/Z, Z18.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z20, Z18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z20.D, P3/M, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P1.B, P3/Z, P1.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z17.D, P1, Z19.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P2.B, P3/Z, P2.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z18.D, P2, Z20.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDA D24, P3, D24, Z17.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
FADDA D24, P3, D24, Z18.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
CBNZ X13, 401c60 <checkSTREAMresults+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	checkSTREAMresults
Source file and lines	stream.c:484-487
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:484-487.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions).

Details

85% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU addition or subtraction instructions are used in vector version.
80% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

24: addition or subtraction

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	54
nb uops	54
loop length	216
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	3
used q registers	0
used v registers	0
used z registers	11
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.75 cycles
front end	6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.83	0.83	0.67	0.67	6.00	2.00	9.00	9.00	9.00	9.00	2.00	2.00	2.00	0.00	0.00
cycles	0.50	0.50	0.83	0.83	0.67	0.67	6.00	2.00	9.00	9.00	9.00	9.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	6.75
Dispatch	9.00
Data deps.	8.00
Overall L1	9.00

Vectorization ratios

INT

all	72%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	85%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	92%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

Vector efficiency ratios

INT

all	77%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	70%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	88%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	96%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	82%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LD1B {Z5.B}, P0/Z, [X8, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X14, X8, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DECW X13, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LD1D {Z6.D}, P3/Z, [X14, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X14, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FSUB Z5.D, Z5.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB Z6.D, Z6.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P1.D, P3/Z, Z5.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z7, Z5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z7.D, P3/M, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P2.D, P3/Z, Z6.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z16, Z6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z16.D, P3/M, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P1.B, P3/Z, P1.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z5.D, P1, Z7.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1B {Z7.B}, P0/Z, [X9, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
EOR P2.B, P3/Z, P2.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z6.D, P2, Z16.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z16.D}, P3/Z, [X14, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X14, X10, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADDA D0, P3, D0, Z5.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
FSUB Z7.D, Z7.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDA D0, P3, D0, Z6.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
FSUB Z16.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P1.D, P3/Z, Z7.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z17, Z7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z17.D, P3/M, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P2.D, P3/Z, Z16.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z18.D, P3/M, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P1.B, P3/Z, P1.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z7.D, P1, Z17.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1B {Z17.B}, P0/Z, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
EOR P2.B, P3/Z, P2.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
ADDVL X11, X11, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
SEL Z16.D, P2, Z18.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LD1D {Z18.D}, P3/Z, [X14, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADDA D1, P3, D1, Z7.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
FSUB Z17.D, Z17.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDA D1, P3, D1, Z16.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
FSUB Z18.D, Z18.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P1.D, P3/Z, Z17.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z19, Z17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z19.D, P3/M, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FCMGE P2.D, P3/Z, Z18.D, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z20, Z18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FNEG Z20.D, P3/M, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P1.B, P3/Z, P1.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z17.D, P1, Z19.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
EOR P2.B, P3/Z, P2.B, P3.B	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
SEL Z18.D, P2, Z20.D, Z18.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADDA D24, P3, D24, Z17.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
FADDA D24, P3, D24, Z18.D	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.25	vect (100.0%)
CBNZ X13, 401c60 <checkSTREAMresults+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code