OV - exec - Function checkSTREAMresults

	Function: checkSTREAMresults	Module: exec	Source: stream.c:456-571 [...]	Coverage (incl. loops): 0.06% \| (excl. loops): 0.00%

/home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c: 456 - 571

--------------------------------------------------------------------------------

456: {

[...]

472: 	for (k=0; k<NTIMES; k++)

473:         {

474:             cj = aj;

475:             bj = scalar*cj;

476:             cj = aj+bj;

477:             aj = bj+scalar*cj;

[...]

484: 	for (j=0; j<STREAM_ARRAY_SIZE; j++) {

485: 		aSumErr += abs(a[j] - aj);

486: 		bSumErr += abs(b[j] - bj);

487: 		cSumErr += abs(c[j] - cj);

488: 		// if (j == 417) printf("Index 417: c[j]: %f, cj: %f\n",c[j],cj);	// MCCALPIN

489: 	}

490: 	aAvgErr = aSumErr / (STREAM_TYPE) STREAM_ARRAY_SIZE;

491: 	bAvgErr = bSumErr / (STREAM_TYPE) STREAM_ARRAY_SIZE;

[...]

506: 	if (abs(aAvgErr/aj) > epsilon) {

507: 		err++;

508: 		printf ("Failed Validation on array a[], AvgRelAbsErr > epsilon (%e)\n",epsilon);

509: 		printf ("     Expected Value: %e, AvgAbsErr: %e, AvgRelAbsErr: %e\n",aj,aAvgErr,abs(aAvgErr)/aj);

510: 		ierr = 0;

511: 		for (j=0; j<STREAM_ARRAY_SIZE; j++) {

512: 			if (abs(a[j]/aj-1.0) > epsilon) {

[...]

522: 		printf("     For array a[], %d errors were found.\n",ierr);

523: 	}

524: 	if (abs(bAvgErr/bj) > epsilon) {

525: 		err++;

526: 		printf ("Failed Validation on array b[], AvgRelAbsErr > epsilon (%e)\n",epsilon);

527: 		printf ("     Expected Value: %e, AvgAbsErr: %e, AvgRelAbsErr: %e\n",bj,bAvgErr,abs(bAvgErr)/bj);

528: 		printf ("     AvgRelAbsErr > Epsilon (%e)\n",epsilon);

529: 		ierr = 0;

530: 		for (j=0; j<STREAM_ARRAY_SIZE; j++) {

531: 			if (abs(b[j]/bj-1.0) > epsilon) {

[...]

541: 		printf("     For array b[], %d errors were found.\n",ierr);

542: 	}

543: 	if (abs(cAvgErr/cj) > epsilon) {

544: 		err++;

545: 		printf ("Failed Validation on array c[], AvgRelAbsErr > epsilon (%e)\n",epsilon);

546: 		printf ("     Expected Value: %e, AvgAbsErr: %e, AvgRelAbsErr: %e\n",cj,cAvgErr,abs(cAvgErr)/cj);

547: 		printf ("     AvgRelAbsErr > Epsilon (%e)\n",epsilon);

548: 		ierr = 0;

549: 		for (j=0; j<STREAM_ARRAY_SIZE; j++) {

550: 			if (abs(c[j]/cj-1.0) > epsilon) {

[...]

560: 		printf("     For array c[], %d errors were found.\n",ierr);

561: 	}

562: 	if (err == 0) {

563: 		printf ("Solution Validates: avg error less than %e on all three arrays\n",epsilon);

[...]

571: }

0x401bb0 STR	D12, [SP, #416]!

0x401bb4 STP	D11, D10, [SP, #16]

0x401bb8 STP	D9, D8, [SP, #32]

0x401bbc STP	X29, X30, [SP, #48]

0x401bc0 STP	X28, X21, [SP, #64]

0x401bc4 STP	X20, X19, [SP, #80]

0x401bc8 ADD	X29, SP, #48

0x401bcc ADDVL	SP, SP, #60

0x401bd0 FMOV	D23, #2.0000000

0x401bd4 FMOV	D0, #3.0000000

0x401bd8 MOVZ	W8, #100

0x401bdc HINT	#0

(14) 0x401be0 FMUL	D1, D23, D0

(14) 0x401be4 SUBS	W8, W8, #2

(14) 0x401be8 FADD	D2, D23, D1

(14) 0x401bec FMADD	D1, D2, D0, D1

(14) 0x401bf0 FMUL	D22, D1, D0

(14) 0x401bf4 FADD	D21, D1, D22

(14) 0x401bf8 FMADD	D23, D21, D0, D22

(14) 0x401bfc B.NE	401be0

0x401c00 RDVL	X12, #1

0x401c04 ADRP	X10,

0x401c08 ADD	X10, X10, #184

0x401c0c MOVZ	W13, #13125

0x401c10 DUP	Z2.D, Z23.D[0]

0x401c14 DUP	Z3.D, Z22.D[0]

0x401c18 DUP	Z4.D, Z21.D[0]

0x401c1c MOVI	D0, #0

0x401c20 PTRUE	P0.B, ALL

0x401c24 PTRUE	P3.D, ALL

0x401c28 MOVI	D24, #0

0x401c2c MOVI	D1, #0

0x401c30 ORR	X11, XZR, XZR

0x401c34 LDP	X8, X9, [X10]

0x401c38 LDR	X10, [X10, #16]

0x401c3c UBFM	X19, X12, #4, #63

0x401c40 ORR	W12, WZR, #1758

0x401c44 MADD	X12, X19, X12, XZR

0x401c48 AND	X12, X12, X13

0x401c4c ORR	X13, XZR, X12

0x401c50 HINT	#0

0x401c54 HINT	#0

0x401c58 HINT	#0

0x401c5c HINT	#0

(15) 0x401c60 LD1B	{Z5.B}, P0/Z, [X8, X11]

(15) 0x401c64 ADD	X14, X8, X11

(15) 0x401c68 DECW	X13, ALL

(15) 0x401c6c LD1D	{Z6.D}, P3/Z, [X14, #1, MUL VL]

(15) 0x401c70 ADD	X14, X9, X11

(15) 0x401c74 FSUB	Z5.D, Z5.D, Z2.D

(15) 0x401c78 FSUB	Z6.D, Z6.D, Z2.D

(15) 0x401c7c FCMGE	P1.D, P3/Z, Z5.D, #0

(15) 0x401c80 MOVPRFX	Z7, Z5

(15) 0x401c84 FNEG	Z7.D, P3/M, Z5.D

(15) 0x401c88 FCMGE	P2.D, P3/Z, Z6.D, #0

(15) 0x401c8c MOVPRFX	Z16, Z6

(15) 0x401c90 FNEG	Z16.D, P3/M, Z6.D

(15) 0x401c94 EOR	P1.B, P3/Z, P1.B, P3.B

(15) 0x401c98 SEL	Z5.D, P1, Z7.D, Z5.D

(15) 0x401c9c LD1B	{Z7.B}, P0/Z, [X9, X11]

(15) 0x401ca0 EOR	P2.B, P3/Z, P2.B, P3.B

(15) 0x401ca4 SEL	Z6.D, P2, Z16.D, Z6.D

(15) 0x401ca8 LD1D	{Z16.D}, P3/Z, [X14, #1, MUL VL]

(15) 0x401cac ADD	X14, X10, X11

(15) 0x401cb0 FADDA	D0, P3, D0, Z5.D

(15) 0x401cb4 FSUB	Z7.D, Z7.D, Z3.D

(15) 0x401cb8 FADDA	D0, P3, D0, Z6.D

(15) 0x401cbc FSUB	Z16.D, Z16.D, Z3.D

(15) 0x401cc0 FCMGE	P1.D, P3/Z, Z7.D, #0

(15) 0x401cc4 MOVPRFX	Z17, Z7

(15) 0x401cc8 FNEG	Z17.D, P3/M, Z7.D

(15) 0x401ccc FCMGE	P2.D, P3/Z, Z16.D, #0

(15) 0x401cd0 MOVPRFX	Z18, Z16

(15) 0x401cd4 FNEG	Z18.D, P3/M, Z16.D

(15) 0x401cd8 EOR	P1.B, P3/Z, P1.B, P3.B

(15) 0x401cdc SEL	Z7.D, P1, Z17.D, Z7.D

(15) 0x401ce0 LD1B	{Z17.B}, P0/Z, [X10, X11]

(15) 0x401ce4 EOR	P2.B, P3/Z, P2.B, P3.B

(15) 0x401ce8 ADDVL	X11, X11, #2

(15) 0x401cec SEL	Z16.D, P2, Z18.D, Z16.D

(15) 0x401cf0 LD1D	{Z18.D}, P3/Z, [X14, #1, MUL VL]

(15) 0x401cf4 FADDA	D1, P3, D1, Z7.D

(15) 0x401cf8 FSUB	Z17.D, Z17.D, Z4.D

(15) 0x401cfc FADDA	D1, P3, D1, Z16.D

(15) 0x401d00 FSUB	Z18.D, Z18.D, Z4.D

(15) 0x401d04 FCMGE	P1.D, P3/Z, Z17.D, #0

(15) 0x401d08 MOVPRFX	Z19, Z17

(15) 0x401d0c FNEG	Z19.D, P3/M, Z17.D

(15) 0x401d10 FCMGE	P2.D, P3/Z, Z18.D, #0

(15) 0x401d14 MOVPRFX	Z20, Z18

(15) 0x401d18 FNEG	Z20.D, P3/M, Z18.D

(15) 0x401d1c EOR	P1.B, P3/Z, P1.B, P3.B

(15) 0x401d20 SEL	Z17.D, P1, Z19.D, Z17.D

(15) 0x401d24 EOR	P2.B, P3/Z, P2.B, P3.B

(15) 0x401d28 SEL	Z18.D, P2, Z20.D, Z18.D

(15) 0x401d2c FADDA	D24, P3, D24, Z17.D

(15) 0x401d30 FADDA	D24, P3, D24, Z18.D

(15) 0x401d34 CBNZ	X13, 401c60

0x401d38 MOVN	X20, #65535

0x401d3c MOVZ	W11, #13125

0x401d40 MOVK	X20, #52411

0x401d44 CMP	X12, X11

0x401d48 B.EQ	401db0

0x401d4c ADD	X11, X12, X20

0x401d50 ADD	X10, X10, X12,LSL #3

0x401d54 ADD	X9, X9, X12,LSL #3

0x401d58 ADD	X8, X8, X12,LSL #3

0x401d5c HINT	#0

(22) 0x401d60 LDR	D2, [X8], #8

(22) 0x401d64 LDR	D4, [X9], #8

(22) 0x401d68 FSUB	D2, D2, S23

(22) 0x401d6c FNEG	D3, D2

(22) 0x401d70 FCMP	D2, #0

(22) 0x401d74 FCSEL	D2, D3, D2, #11

(22) 0x401d78 FADD	D0, D0, D2

(22) 0x401d7c FSUB	D2, D4, S22

(22) 0x401d80 FNEG	D3, D2

(22) 0x401d84 FCMP	D2, #0

(22) 0x401d88 FCSEL	D2, D3, D2, #11

(22) 0x401d8c FADD	D1, D1, D2

(22) 0x401d90 LDR	D2, [X10], #8

(22) 0x401d94 FSUB	D2, D2, S21

(22) 0x401d98 FNEG	D3, D2

(22) 0x401d9c FCMP	D2, #0

(22) 0x401da0 FCSEL	D2, D3, D2, #11

(22) 0x401da4 ADDS	X11, X11, #1

(22) 0x401da8 FADD	D24, D24, D2

(22) 0x401dac B.CC	401d60

0x401db0 MOVZ	X8, #41600

0x401db4 ADRP	X21,

0x401db8 ADD	X21, X21, #736

0x401dbc MOVK	X8, #16841

0x401dc0 FMOV	D12, X8

0x401dc4 ADRP	X8,

0x401dc8 LDR	D8, [X8, #736]

0x401dcc SUB	X8, X29, #48

0x401dd0 STR	Z21, [X8, #511, MUL VL]

0x401dd4 STR	Z22, [X8, #510, MUL VL]

0x401dd8 FDIV	D9, D0, D12

0x401ddc FDIV	D10, D1, D12

0x401de0 FDIV	D0, D9, D23

0x401de4 FNEG	D1, D0

0x401de8 FCMP	D0, #0

0x401dec FCSEL	D11, D1, D0, #11

0x401df0 FCMP	D11, D8

0x401df4 B.LE	401f44

0x401df8 FMOV	D0, D8

0x401dfc ADRP	X0,

0x401e00 ADD	X0, X0, #2792

0x401e04 STR	Z24, [X8, #508, MUL VL]

0x401e08 STR	Z23, [X8, #509, MUL VL]

0x401e0c BL	400960

0x401e10 SUB	X8, X29, #48

0x401e14 FNEG	D0, D9

0x401e18 FCMP	D9, #0

0x401e1c ADRP	X0,

0x401e20 ADD	X0, X0, #2853

0x401e24 LDR	Z1, [X8, #509, MUL VL]

0x401e28 FCSEL	D0, D9, D0, #10

0x401e2c FDIV	D2, D0, D1

0x401e30 FMOV	D1, D9

0x401e34 LDR	Z0, [X8, #509, MUL VL]

0x401e38 BL	400960

0x401e3c SUB	X8, X29, #48

0x401e40 PTRUE	P2.D, ALL

0x401e44 ORR	W9, WZR, #1758

0x401e48 DUP	Z0.D, #0

0x401e4c MOVZ	W10, #13125

0x401e50 FDUP	Z2.D, #240

0x401e54 DUP	Z4.D, #1

0x401e58 LDR	Z18, [X8, #509, MUL VL]

0x401e5c ADRP	X8,

0x401e60 MADD	X9, X19, X9, XZR

0x401e64 LD1RD	{Z3.D}, P2/Z, [X21]

0x401e68 LDR	X8, [X8, #184]

0x401e6c ORR	Z5.D, Z0.D, Z0.D

0x401e70 AND	X9, X9, X10

0x401e74 ORR	X10, XZR, X9

0x401e78 ORR	X11, XZR, X8

0x401e7c DUP	Z1.D, Z18.D[0]

(20) 0x401e80 LD1D	{Z6.D}, P2/Z, [X11, MUL VL]

(20) 0x401e84 LD1D	{Z7.D}, P2/Z, [X11, #1, MUL VL]

(20) 0x401e88 ADDVL	X11, X11, #2

(20) 0x401e8c DECW	X10, ALL

(20) 0x401e90 FDIV	Z6.D, P2/M, Z6.D, Z1.D

(20) 0x401e94 FADD	Z6.D, Z6.D, Z2.D

(20) 0x401e98 FDIV	Z7.D, P2/M, Z7.D, Z1.D

(20) 0x401e9c FADD	Z7.D, Z7.D, Z2.D

(20) 0x401ea0 FCMGE	P0.D, P2/Z, Z6.D, #0

(20) 0x401ea4 FCMGE	P1.D, P2/Z, Z7.D, #0

(20) 0x401ea8 MOVPRFX	Z16, Z6

(20) 0x401eac FNEG	Z16.D, P2/M, Z6.D

(20) 0x401eb0 MOVPRFX	Z17, Z7

(20) 0x401eb4 FNEG	Z17.D, P2/M, Z7.D

(20) 0x401eb8 EOR	P0.B, P2/Z, P0.B, P2.B

(20) 0x401ebc EOR	P1.B, P2/Z, P1.B, P2.B

(20) 0x401ec0 SEL	Z6.D, P0, Z16.D, Z6.D

(20) 0x401ec4 SEL	Z7.D, P1, Z17.D, Z7.D

(20) 0x401ec8 FCMGT	P0.D, P2/Z, Z6.D, Z3.D

(20) 0x401ecc FCMGT	P1.D, P2/Z, Z7.D, Z3.D

(20) 0x401ed0 ADD	Z0.D, P0/M, Z0.D, Z4.D

(20) 0x401ed4 ADD	Z5.D, P1/M, Z5.D, Z4.D

(20) 0x401ed8 CBNZ	X10, 401e80

0x401edc ADD	Z0.D, Z5.D, Z0.D

0x401ee0 MOVZ	W10, #13125

0x401ee4 UADDV	D0, P2, Z0.D

0x401ee8 FMOV	X1, D0

0x401eec CMP	X9, X10

0x401ef0 B.EQ	401f28

0x401ef4 FMOV	D0, #-1.0000000

0x401ef8 ADD	X10, X9, X20

0x401efc ADD	X8, X8, X9,LSL #3

(21) 0x401f00 LDR	D1, [X8], #8

(21) 0x401f04 FDIV	D1, D1, D18

(21) 0x401f08 FADD	D1, D1, D0

(21) 0x401f0c FNEG	D2, D1

(21) 0x401f10 FCMP	D1, #0

(21) 0x401f14 FCSEL	D1, D2, D1, #11

(21) 0x401f18 FCMP	D1, D8

(21) 0x401f1c CSINC	W1, W1, W1, #13

(21) 0x401f20 ADDS	X10, X10, #1

(21) 0x401f24 B.CC	401f00

0x401f28 ADRP	X0,

0x401f2c ADD	X0, X0, #2911

0x401f30 BL	400960

0x401f34 SUB	X8, X29, #48

0x401f38 LDR	Z21, [X8, #511, MUL VL]

0x401f3c LDR	Z22, [X8, #510, MUL VL]

0x401f40 LDR	Z24, [X8, #508, MUL VL]

0x401f44 FDIV	D0, D10, D22

0x401f48 FNEG	D1, D0

0x401f4c FDIV	D9, D24, D12

0x401f50 FCMP	D0, #0

0x401f54 FCSEL	D0, D1, D0, #11

0x401f58 FCMP	D0, D8

0x401f5c B.LE	4020d8

0x401f60 FMOV	D0, D8

0x401f64 ADRP	X0,

0x401f68 ADD	X0, X0, #2954

0x401f6c BL	400960

0x401f70 SUB	X8, X29, #48

0x401f74 FNEG	D0, D10

0x401f78 FCMP	D10, #0

0x401f7c ADRP	X0,

0x401f80 ADD	X0, X0, #2853

0x401f84 LDR	Z1, [X8, #510, MUL VL]

0x401f88 FCSEL	D0, D10, D0, #10

0x401f8c FDIV	D2, D0, D1

0x401f90 FMOV	D1, D10

0x401f94 LDR	Z0, [X8, #510, MUL VL]

0x401f98 BL	400960

0x401f9c FMOV	D0, D8

0x401fa0 ADRP	X0,

0x401fa4 ADD	X0, X0, #3015

0x401fa8 BL	400960

0x401fac SUB	X8, X29, #48

0x401fb0 PTRUE	P2.D, ALL

0x401fb4 ORR	W9, WZR, #1758

0x401fb8 DUP	Z0.D, #0

0x401fbc MOVZ	W10, #13125

0x401fc0 FDUP	Z2.D, #240

0x401fc4 DUP	Z4.D, #1

0x401fc8 LDR	Z18, [X8, #510, MUL VL]

0x401fcc ADRP	X8,

0x401fd0 MADD	X9, X19, X9, XZR

0x401fd4 LD1RD	{Z3.D}, P2/Z, [X21]

0x401fd8 LDR	X8, [X8, #192]

0x401fdc ORR	Z5.D, Z0.D, Z0.D

0x401fe0 AND	X9, X9, X10

0x401fe4 ORR	X10, XZR, X9

0x401fe8 ORR	X11, XZR, X8

0x401fec DUP	Z1.D, Z18.D[0]

0x401ff0 HINT	#0

0x401ff4 HINT	#0

0x401ff8 HINT	#0

0x401ffc HINT	#0

(18) 0x402000 LD1D	{Z6.D}, P2/Z, [X11, MUL VL]

(18) 0x402004 LD1D	{Z7.D}, P2/Z, [X11, #1, MUL VL]

(18) 0x402008 ADDVL	X11, X11, #2

(18) 0x40200c DECW	X10, ALL

(18) 0x402010 FDIV	Z6.D, P2/M, Z6.D, Z1.D

(18) 0x402014 FADD	Z6.D, Z6.D, Z2.D

(18) 0x402018 FDIV	Z7.D, P2/M, Z7.D, Z1.D

(18) 0x40201c FADD	Z7.D, Z7.D, Z2.D

(18) 0x402020 FCMGE	P0.D, P2/Z, Z6.D, #0

(18) 0x402024 FCMGE	P1.D, P2/Z, Z7.D, #0

(18) 0x402028 MOVPRFX	Z16, Z6

(18) 0x40202c FNEG	Z16.D, P2/M, Z6.D

(18) 0x402030 MOVPRFX	Z17, Z7

(18) 0x402034 FNEG	Z17.D, P2/M, Z7.D

(18) 0x402038 EOR	P0.B, P2/Z, P0.B, P2.B

(18) 0x40203c EOR	P1.B, P2/Z, P1.B, P2.B

(18) 0x402040 SEL	Z6.D, P0, Z16.D, Z6.D

(18) 0x402044 SEL	Z7.D, P1, Z17.D, Z7.D

(18) 0x402048 FCMGT	P0.D, P2/Z, Z6.D, Z3.D

(18) 0x40204c FCMGT	P1.D, P2/Z, Z7.D, Z3.D

(18) 0x402050 ADD	Z0.D, P0/M, Z0.D, Z4.D

(18) 0x402054 ADD	Z5.D, P1/M, Z5.D, Z4.D

(18) 0x402058 CBNZ	X10, 402000

0x40205c ADD	Z0.D, Z5.D, Z0.D

0x402060 MOVZ	W10, #13125

0x402064 UADDV	D0, P2, Z0.D

0x402068 FMOV	X1, D0

0x40206c CMP	X9, X10

0x402070 B.EQ	4020a8

0x402074 FMOV	D0, #-1.0000000

0x402078 ADD	X10, X9, X20

0x40207c ADD	X8, X8, X9,LSL #3

(19) 0x402080 LDR	D1, [X8], #8

(19) 0x402084 FDIV	D1, D1, D18

(19) 0x402088 FADD	D1, D1, D0

(19) 0x40208c FNEG	D2, D1

(19) 0x402090 FCMP	D1, #0

(19) 0x402094 FCSEL	D1, D2, D1, #11

(19) 0x402098 FCMP	D1, D8

(19) 0x40209c CSINC	W1, W1, W1, #13

(19) 0x4020a0 ADDS	X10, X10, #1

(19) 0x4020a4 B.CC	402080

0x4020a8 ADRP	X0, 4020a8

0x4020ac ADD	X0, X0, #3049

0x4020b0 BL	400960

0x4020b4 SUB	X8, X29, #48

0x4020b8 LDR	Z0, [X8, #511, MUL VL]

0x4020bc FDIV	D0, D9, D0

0x4020c0 FNEG	D1, D0

0x4020c4 FCMP	D0, #0

0x4020c8 FCSEL	D0, D1, D0, #11

0x4020cc FCMP	D0, D8

0x4020d0 B.GT	4020f0

0x4020d4 B	402284

0x4020d8 FDIV	D0, D9, D21

0x4020dc FNEG	D1, D0

0x4020e0 FCMP	D0, #0

0x4020e4 FCSEL	D0, D1, D0, #11

0x4020e8 FCMP	D0, D8

0x4020ec B.LE	402250

0x4020f0 FMOV	D0, D8

0x4020f4 ADRP	X0, 4020f4

0x4020f8 ADD	X0, X0, #3092

0x4020fc BL	400960

0x402100 SUB	X8, X29, #48

0x402104 FNEG	D0, D9

0x402108 FCMP	D9, #0

0x40210c ADRP	X0, 40210c

0x402110 ADD	X0, X0, #2853

0x402114 LDR	Z1, [X8, #511, MUL VL]

0x402118 FCSEL	D0, D9, D0, #10

0x40211c FDIV	D2, D0, D1

0x402120 FMOV	D1, D9

0x402124 LDR	Z0, [X8, #511, MUL VL]

0x402128 BL	400960

0x40212c FMOV	D0, D8

0x402130 ADRP	X0, 402130

0x402134 ADD	X0, X0, #3015

0x402138 BL	400960

0x40213c SUB	X8, X29, #48

0x402140 PTRUE	P2.D, ALL

0x402144 ORR	W9, WZR, #1758

0x402148 DUP	Z0.D, #0

0x40214c MOVZ	W10, #13125

0x402150 FDUP	Z2.D, #240

0x402154 DUP	Z4.D, #1

0x402158 LDR	Z18, [X8, #511, MUL VL]

0x40215c ADRP	X8,

0x402160 MADD	X9, X19, X9, XZR

0x402164 LD1RD	{Z3.D}, P2/Z, [X21]

0x402168 LDR	X8, [X8, #200]

0x40216c ORR	Z5.D, Z0.D, Z0.D

0x402170 AND	X9, X9, X10

0x402174 ORR	X10, XZR, X9

0x402178 ORR	X11, XZR, X8

0x40217c DUP	Z1.D, Z18.D[0]

(16) 0x402180 LD1D	{Z6.D}, P2/Z, [X11, MUL VL]

(16) 0x402184 LD1D	{Z7.D}, P2/Z, [X11, #1, MUL VL]

(16) 0x402188 ADDVL	X11, X11, #2

(16) 0x40218c DECW	X10, ALL

(16) 0x402190 FDIV	Z6.D, P2/M, Z6.D, Z1.D

(16) 0x402194 FADD	Z6.D, Z6.D, Z2.D

(16) 0x402198 FDIV	Z7.D, P2/M, Z7.D, Z1.D

(16) 0x40219c FADD	Z7.D, Z7.D, Z2.D

(16) 0x4021a0 FCMGE	P0.D, P2/Z, Z6.D, #0

(16) 0x4021a4 FCMGE	P1.D, P2/Z, Z7.D, #0

(16) 0x4021a8 MOVPRFX	Z16, Z6

(16) 0x4021ac FNEG	Z16.D, P2/M, Z6.D

(16) 0x4021b0 MOVPRFX	Z17, Z7

(16) 0x4021b4 FNEG	Z17.D, P2/M, Z7.D

(16) 0x4021b8 EOR	P0.B, P2/Z, P0.B, P2.B

(16) 0x4021bc EOR	P1.B, P2/Z, P1.B, P2.B

(16) 0x4021c0 SEL	Z6.D, P0, Z16.D, Z6.D

(16) 0x4021c4 SEL	Z7.D, P1, Z17.D, Z7.D

(16) 0x4021c8 FCMGT	P0.D, P2/Z, Z6.D, Z3.D

(16) 0x4021cc FCMGT	P1.D, P2/Z, Z7.D, Z3.D

(16) 0x4021d0 ADD	Z0.D, P0/M, Z0.D, Z4.D

(16) 0x4021d4 ADD	Z5.D, P1/M, Z5.D, Z4.D

(16) 0x4021d8 CBNZ	X10, 402180

0x4021dc ADD	Z0.D, Z5.D, Z0.D

0x4021e0 MOVZ	W10, #13125

0x4021e4 UADDV	D0, P2, Z0.D

0x4021e8 FMOV	X1, D0

0x4021ec CMP	X9, X10

0x4021f0 B.EQ	402228

0x4021f4 FMOV	D0, #-1.0000000

0x4021f8 ADD	X10, X9, X20

0x4021fc ADD	X8, X8, X9,LSL #3

(17) 0x402200 LDR	D1, [X8], #8

(17) 0x402204 FDIV	D1, D1, D18

(17) 0x402208 FADD	D1, D1, D0

(17) 0x40220c FNEG	D2, D1

(17) 0x402210 FCMP	D1, #0

(17) 0x402214 FCSEL	D1, D2, D1, #11

(17) 0x402218 FCMP	D1, D8

(17) 0x40221c CSINC	W1, W1, W1, #13

(17) 0x402220 ADDS	X10, X10, #1

(17) 0x402224 B.CC	402200

0x402228 ADRP	X0, 402228

0x40222c ADD	X0, X0, #3153

0x402230 ADDVL	SP, SP, #4

0x402234 LDP	D9, D8, [SP, #32]

0x402238 LDP	D11, D10, [SP, #16]

0x40223c LDP	X20, X19, [SP, #80]

0x402240 LDP	X28, X21, [SP, #64]

0x402244 LDP	X29, X30, [SP, #48]

0x402248 LDR	D12, [SP], #96

0x40224c B	400960

0x402250 FCMP	D11, D8

0x402254 B.GT	402284

0x402258 ADRP	X0, 402258

0x40225c ADD	X0, X0, #3196

0x402260 FMOV	D0, D8

0x402264 ADDVL	SP, SP, #4

0x402268 LDP	D9, D8, [SP, #32]

0x40226c LDP	D11, D10, [SP, #16]

0x402270 LDP	X20, X19, [SP, #80]

0x402274 LDP	X28, X21, [SP, #64]

0x402278 LDP	X29, X30, [SP, #48]

0x40227c LDR	D12, [SP], #96

0x402280 B	400960

0x402284 ADDVL	SP, SP, #4

0x402288 LDP	D9, D8, [SP, #32]

0x40228c LDP	D11, D10, [SP, #16]

0x402290 LDP	X20, X19, [SP, #80]

0x402294 LDP	X28, X21, [SP, #64]

0x402298 LDP	X29, X30, [SP, #48]

0x40229c LDR	D12, [SP], #96

0x4022a0 RET

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:394	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:456-571
Module	exec

The function is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:456,472-477,484-491,506-512,522-531,541-550,560-563,571.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 34.97 to 11.17 cycles (3.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 61% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 34.97 to 24.96 cycles (1.40x speedup).

Details

21% of VPU instructions are used in vector version (process two or more data elements in vector registers):

59% of VPU loads are used in vector version.
60% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
9% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 34.97 to 5.00 cycles (6.99x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 10 occurrences►
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:508
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:509
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:522
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:526
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:527
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:528
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:541
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:545
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:546
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:547

Matching between your function (in the source code) and the binary function

The binary function is composed of 10 FP arithmetical operations:

10: divide

The binary function is loading 552 bytes. The binary function is storing 152 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	264
nb uops	254
loop length	1056
used w registers	7
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	12
used q registers	0
used v registers	0
used z registers	11
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.75 cycles
front end	31.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	19.00	19.00	19.00	19.00	19.00	19.00	22.75	22.75	22.75	22.75	16.67	16.67	16.67	1.50	1.50
cycles	11.50	11.50	19.00	19.00	19.00	19.00	19.00	19.00	22.75	22.75	22.75	22.75	16.67	16.67	16.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

17.51-34.97

Cycles summary

Front-end	31.75
Dispatch	22.75
DIV/SQRT	17.51-34.97
Overall L1	31.75-34.97

Vectorization ratios

INT

all	32%
load	59%
store	60%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	0%
other	19%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	21%
load	59%
store	60%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	0%
div/sqrt	0%
other	9%

Vector efficiency ratios

INT

all	68%
load	89%
store	95%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	50%
other	56%

all	47%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	47%

INT+FP

all	61%
load	89%
store	95%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	50%
div/sqrt	50%
other	51%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.97 cycles. At this rate:

16% of peak load performance is reached (15.79 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 401bb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STR D12, [SP, #416]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADDVL SP, SP, #60	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
FMOV D23, #2.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D0, #3.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ W8, #100	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
RDVL X12, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADRP X10, <420c04>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #184	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W13, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP Z2.D, Z23.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z3.D, Z22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z4.D, Z21.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
PTRUE P0.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
PTRUE P3.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
MOVI D24, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X11, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X8, X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X19, X12, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W12, WZR, #1758	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X12, X19, X12, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
AND X12, X12, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X13, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
MOVN X20, #65535	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W11, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVK X20, #52411	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X12, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401db0 <checkSTREAMresults+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X12, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, X10, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X8, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
MOVZ X8, #41600	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X21, <402db4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X21, #736	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X8, #16841	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D12, X8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X8, <402dc4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D8, [X8, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z21, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z22, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FDIV D9, D0, D12	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FDIV D10, D1, D12	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FDIV D0, D9, D23	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D11, D1, D0, #11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D11, D8	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.LE 401f44 <checkSTREAMresults+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, <402dfc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2792	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z24, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z23, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FNEG D0, D9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D9, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADRP X0, <402e1c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2853	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR Z1, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCSEL D0, D9, D0, #10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMOV D1, D9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR Z0, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PTRUE P2.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ORR W9, WZR, #1758	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
LDR Z18, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADRP X8, <420e5c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X19, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LD1RD {Z3.D}, P2/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X8, [X8, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z1.D, Z18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UADDV D0, P2, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.75	0.25	0.75	0	0	0	0	0	6	1	vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401f28 <checkSTREAMresults+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X9, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <402f28>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2911	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Z21, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z22, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z24, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FDIV D0, D10, D22	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D9, D24, D12	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, D8	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.LE 4020d8 <checkSTREAMresults+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, <402f64>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2954	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FNEG D0, D10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D10, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADRP X0, <402f7c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2853	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR Z1, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCSEL D0, D10, D0, #10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMOV D1, D10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR Z0, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, <402fa0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3015	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PTRUE P2.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ORR W9, WZR, #1758	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
LDR Z18, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADRP X8, <420fcc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X19, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LD1RD {Z3.D}, P2/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X8, [X8, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z1.D, Z18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UADDV D0, P2, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.75	0.25	0.75	0	0	0	0	0	6	1	vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4020a8 <checkSTREAMresults+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X9, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, 4020a8 <checkSTREAMresults+0x4f8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3049	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FDIV D0, D9, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, D8	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GT 4020f0 <checkSTREAMresults+0x540>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 402284 <checkSTREAMresults+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D0, D9, D21	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, D8	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.LE 402250 <checkSTREAMresults+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, 4020f4 <checkSTREAMresults+0x544>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3092	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FNEG D0, D9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D9, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADRP X0, 40210c <checkSTREAMresults+0x55c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2853	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR Z1, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCSEL D0, D9, D0, #10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMOV D1, D9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, 402130 <checkSTREAMresults+0x580>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3015	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PTRUE P2.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ORR W9, WZR, #1758	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
LDR Z18, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADRP X8, <42015c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X19, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LD1RD {Z3.D}, P2/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X8, [X8, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z1.D, Z18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UADDV D0, P2, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.75	0.25	0.75	0	0	0	0	0	6	1	vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402228 <checkSTREAMresults+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X9, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, 402228 <checkSTREAMresults+0x678>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3153	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADDVL SP, SP, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D12, [SP], #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
B 400960 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D11, D8	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GT 402284 <checkSTREAMresults+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, 402258 <checkSTREAMresults+0x6a8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3196	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADDVL SP, SP, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D12, [SP], #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
B 400960 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D12, [SP], #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:456-571
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

21% of VPU instructions are used in vector version (process two or more data elements in vector registers):

59% of VPU loads are used in vector version.
60% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
9% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 34.97 to 5.00 cycles (6.99x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 10 occurrences►
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:508
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:509
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:522
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:526
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:527
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:528
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:541
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:545
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:546
- /home/eoseret/Tools/QaaS/qaas_runs/175-492-1446/intel/stream/build/stream/src/stream.c:547

Matching between your function (in the source code) and the binary function

The binary function is composed of 10 FP arithmetical operations:

10: divide

The binary function is loading 552 bytes. The binary function is storing 152 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	264
nb uops	254
loop length	1056
used w registers	7
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	12
used q registers	0
used v registers	0
used z registers	11
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.75 cycles
front end	31.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	19.00	19.00	19.00	19.00	19.00	19.00	22.75	22.75	22.75	22.75	16.67	16.67	16.67	1.50	1.50
cycles	11.50	11.50	19.00	19.00	19.00	19.00	19.00	19.00	22.75	22.75	22.75	22.75	16.67	16.67	16.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

17.51-34.97

Cycles summary

Front-end	31.75
Dispatch	22.75
DIV/SQRT	17.51-34.97
Overall L1	31.75-34.97

Vectorization ratios

INT

all	32%
load	59%
store	60%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	0%
other	19%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	21%
load	59%
store	60%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	0%
div/sqrt	0%
other	9%

Vector efficiency ratios

INT

all	68%
load	89%
store	95%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	50%
other	56%

all	47%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	47%

INT+FP

all	61%
load	89%
store	95%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	50%
div/sqrt	50%
other	51%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.97 cycles. At this rate:

16% of peak load performance is reached (15.79 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 401bb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STR D12, [SP, #416]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADDVL SP, SP, #60	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
FMOV D23, #2.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D0, #3.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ W8, #100	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
RDVL X12, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADRP X10, <420c04>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #184	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W13, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP Z2.D, Z23.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z3.D, Z22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z4.D, Z21.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
PTRUE P0.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
PTRUE P3.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
MOVI D24, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X11, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X8, X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X19, X12, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W12, WZR, #1758	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X12, X19, X12, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
AND X12, X12, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X13, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
MOVN X20, #65535	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W11, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVK X20, #52411	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X12, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401db0 <checkSTREAMresults+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X12, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, X10, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X8, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
MOVZ X8, #41600	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X21, <402db4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X21, #736	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVK X8, #16841	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D12, X8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X8, <402dc4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D8, [X8, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z21, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z22, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FDIV D9, D0, D12	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FDIV D10, D1, D12	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FDIV D0, D9, D23	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D11, D1, D0, #11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D11, D8	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.LE 401f44 <checkSTREAMresults+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, <402dfc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2792	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z24, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z23, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FNEG D0, D9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D9, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADRP X0, <402e1c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2853	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR Z1, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCSEL D0, D9, D0, #10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMOV D1, D9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR Z0, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PTRUE P2.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ORR W9, WZR, #1758	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
LDR Z18, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADRP X8, <420e5c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X19, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LD1RD {Z3.D}, P2/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X8, [X8, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z1.D, Z18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UADDV D0, P2, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.75	0.25	0.75	0	0	0	0	0	6	1	vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 401f28 <checkSTREAMresults+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X9, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <402f28>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2911	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Z21, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z22, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z24, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FDIV D0, D10, D22	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D9, D24, D12	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, D8	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.LE 4020d8 <checkSTREAMresults+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, <402f64>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2954	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FNEG D0, D10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D10, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADRP X0, <402f7c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2853	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR Z1, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCSEL D0, D10, D0, #10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMOV D1, D10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR Z0, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, <402fa0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3015	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PTRUE P2.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ORR W9, WZR, #1758	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
LDR Z18, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADRP X8, <420fcc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X19, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LD1RD {Z3.D}, P2/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X8, [X8, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z1.D, Z18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UADDV D0, P2, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.75	0.25	0.75	0	0	0	0	0	6	1	vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4020a8 <checkSTREAMresults+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X9, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, 4020a8 <checkSTREAMresults+0x4f8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3049	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FDIV D0, D9, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, D8	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GT 4020f0 <checkSTREAMresults+0x540>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 402284 <checkSTREAMresults+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D0, D9, D21	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D0, D8	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.LE 402250 <checkSTREAMresults+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, 4020f4 <checkSTREAMresults+0x544>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3092	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FNEG D0, D9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D9, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADRP X0, 40210c <checkSTREAMresults+0x55c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #2853	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR Z1, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCSEL D0, D9, D0, #10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMOV D1, D9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X0, 402130 <checkSTREAMresults+0x580>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3015	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PTRUE P2.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ORR W9, WZR, #1758	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (6.3%)
LDR Z18, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADRP X8, <42015c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X19, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LD1RD {Z3.D}, P2/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X8, [X8, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
DUP Z1.D, Z18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UADDV D0, P2, Z0.D	1	0	0	0	0	0	0	0	0	0.25	0.75	0.25	0.75	0	0	0	0	0	6	1	vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 402228 <checkSTREAMresults+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X9, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, 402228 <checkSTREAMresults+0x678>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3153	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADDVL SP, SP, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D12, [SP], #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
B 400960 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D11, D8	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GT 402284 <checkSTREAMresults+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, 402258 <checkSTREAMresults+0x6a8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3196	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADDVL SP, SP, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D12, [SP], #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
B 400960 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D12, [SP], #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼checkSTREAMresults–	0.06	0.01
○Loop 15 - stream.c:484-487 - exec	0.06	1.10
○Loop 14 - stream.c:472-477 - exec	0.00	0.00
○Loop 22 - stream.c:484-487 - exec	0.00	0.00
○Loop 18 - stream.c:530-531 - exec	0.00	0.00
○Loop 17 - stream.c:549-550 - exec	0.00	0.00
○Loop 21 - stream.c:511-512 - exec	0.00	0.00
○Loop 16 - stream.c:549-550 - exec	0.00	0.00
○Loop 20 - stream.c:511-512 - exec	0.00	0.00
○Loop 19 - stream.c:530-531 - exec	0.00	0.00

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Expensive FP math instructions/calls

CALL instructions

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Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

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Cycles summary

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ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code