OV - exec - Loop 8

	Loop Id: 8	Module: exec	Source: stream.c:334-336	Coverage: 0.00%

0x401494 MADD	X14, X3, X1, X0

0x401498 ADD	X11, X3, X14

0x40149c CMP	X14, X11

0x4014a0 B.GE	4015f0

0x4014a4 ADRP	X5, 4014a4

0x4014a8 SUB	X4, X11, X14

0x4014ac LDR	D31, [X20]

0x4014b0 ANDS	X6, X4, #4224

0x4014b4 LDR	X7, [X5, #1544]

0x4014b8 LDP	X12, X13, [X7]

0x4014bc B.EQ	401568

0x4014c0 CMP	X6, #1

0x4014c4 B.EQ	401550

0x4014c8 CMP	X6, #2

0x4014cc B.EQ	401540

0x4014d0 CMP	X6, #3

0x4014d4 B.EQ	401530

0x4014d8 CMP	X6, #4

0x4014dc B.EQ	401520

0x4014e0 CMP	X6, #5

0x4014e4 B.EQ	401510

0x4014e8 CMP	X6, #6

0x4014ec B.EQ	401500

0x4014f0 LDR	D21, [X13, X14,LSL #3]

0x4014f4 FMUL	D0, D21, D31

0x4014f8 STR	D0, [X12, X14,LSL #3]

0x4014fc ADD	X14, X14, #1

0x401500 LDR	D20, [X13, X14,LSL #3]

0x401504 FMUL	D1, D20, D31

0x401508 STR	D1, [X12, X14,LSL #3]

0x40150c ADD	X14, X14, #1

0x401510 LDR	D19, [X13, X14,LSL #3]

0x401514 FMUL	D2, D19, D31

0x401518 STR	D2, [X12, X14,LSL #3]

0x40151c ADD	X14, X14, #1

0x401520 LDR	D18, [X13, X14,LSL #3]

0x401524 FMUL	D3, D18, D31

0x401528 STR	D3, [X12, X14,LSL #3]

0x40152c ADD	X14, X14, #1

0x401530 LDR	D17, [X13, X14,LSL #3]

0x401534 FMUL	D4, D17, D31

0x401538 STR	D4, [X12, X14,LSL #3]

0x40153c ADD	X14, X14, #1

0x401540 LDR	D16, [X13, X14,LSL #3]

0x401544 FMUL	D5, D16, D31

0x401548 STR	D5, [X12, X14,LSL #3]

0x40154c ADD	X14, X14, #1

0x401550 LDR	D7, [X13, X14,LSL #3]

0x401554 FMUL	D6, D7, D31

0x401558 STR	D6, [X12, X14,LSL #3]

0x40155c ADD	X14, X14, #1

0x401560 CMP	X11, X14

0x401564 B.EQ	4015f0

  (9) 0x401568 LDR	D22, [X13, X14,LSL #3]

  (9) 0x40156c ADD	X15, X14, #1

  (9) 0x401570 ADD	X10, X14, #2

  (9) 0x401574 ADD	X9, X14, #3

  (9) 0x401578 ADD	X8, X14, #4

  (9) 0x40157c ADD	X16, X14, #5

  (9) 0x401580 ADD	X17, X14, #6

  (9) 0x401584 ADD	X18, X14, #7

  (9) 0x401588 FMUL	D23, D22, D31

  (9) 0x40158c STR	D23, [X12, X14,LSL #3]

  (9) 0x401590 ADD	X14, X14, #8

  (9) 0x401594 LDR	D24, [X13, X15,LSL #3]

  (9) 0x401598 FMUL	D25, D24, D31

  (9) 0x40159c STR	D25, [X12, X15,LSL #3]

  (9) 0x4015a0 LDR	D26, [X13, X10,LSL #3]

  (9) 0x4015a4 FMUL	D27, D26, D31

  (9) 0x4015a8 STR	D27, [X12, X10,LSL #3]

  (9) 0x4015ac LDR	D28, [X13, X9,LSL #3]

  (9) 0x4015b0 FMUL	D29, D28, D31

  (9) 0x4015b4 STR	D29, [X12, X9,LSL #3]

  (9) 0x4015b8 LDR	D30, [X13, X8,LSL #3]

  (9) 0x4015bc FMUL	D21, D30, D31

  (9) 0x4015c0 STR	D21, [X12, X8,LSL #3]

  (9) 0x4015c4 LDR	D0, [X13, X16,LSL #3]

  (9) 0x4015c8 FMUL	D20, D0, D31

  (9) 0x4015cc STR	D20, [X12, X16,LSL #3]

  (9) 0x4015d0 LDR	D1, [X13, X17,LSL #3]

  (9) 0x4015d4 FMUL	D19, D1, D31

  (9) 0x4015d8 STR	D19, [X12, X17,LSL #3]

  (9) 0x4015dc LDR	D2, [X13, X18,LSL #3]

  (9) 0x4015e0 FMUL	D18, D2, D31

  (9) 0x4015e4 STR	D18, [X12, X18,LSL #3]

  (9) 0x4015e8 CMP	X11, X14

  (9) 0x4015ec B.NE	401568

0x4015f0 LDP	X19, X20, [SP, #16]

0x4015f4 LDP	X29, X30, [SP], #32

0x4015f8 RET

0x4015fc ADD	X3, X3, #1

0x401600 MOVZ	X0, #0

0x401604 B	401494

/home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c: 334 - 336

--------------------------------------------------------------------------------

334: #pragma omp parallel for

335: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

336: 	    b[j] = scalar*c[j];

Coverage (%)	Name	Source Location	Module
►80.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6
►20.00+	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.43
CQA speedup if FP arith vectorized	1.32
CQA speedup if fully vectorized	3.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main._omp_fn.5
Source	stream.c:334-336
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.38
CQA cycles if no scalar integer	5.17
CQA cycles if FP arith vectorized	5.58
CQA cycles if fully vectorized	1.88
Front-end cycles	7.38
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	5.50
P3 cycles	5.50
P4 cycles	5.50
P5 cycles	5.50
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	6.50
P11 cycles	6.17
P12 cycles	6.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	7.00
Nb stack references	2.00
FLOP/cycle	0.95
Nb FLOP add-sub	0.00
Nb FLOP mul	7.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.86
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.71
Vector-efficiency ratio load	27.78
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.43
CQA speedup if FP arith vectorized	1.32
CQA speedup if fully vectorized	3.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main._omp_fn.5
Source	stream.c:334-336
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.38
CQA cycles if no scalar integer	5.17
CQA cycles if FP arith vectorized	5.58
CQA cycles if fully vectorized	1.88
Front-end cycles	7.38
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	5.50
P3 cycles	5.50
P4 cycles	5.50
P5 cycles	5.50
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	6.50
P11 cycles	6.17
P12 cycles	6.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	7.00
Nb stack references	2.00
FLOP/cycle	0.95
Nb FLOP add-sub	0.00
Nb FLOP mul	7.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.86
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.71
Vector-efficiency ratio load	27.78
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.5
Source file and lines	stream.c:334-336
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:334-336.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.38 to 5.17 cycles (1.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.38 to 1.87 cycles (3.93x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7 FP arithmetical operations:

7: multiply

The binary loop is loading 120 bytes. The binary loop is storing 56 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	59
nb uops	59
loop length	236
used w registers	0
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	15
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.38 cycles
front end	7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	3.50	3.50	6.50	6.17	6.33	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	3.50	3.50	6.50	6.17	6.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.38
Dispatch	6.50
Overall L1	7.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	27%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	27%
store	25%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.38 cycles. At this rate:

16% of peak load performance is reached (16.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.59 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.38 to 6.50 cycles (1.13x speedup).

ASM code

In the binary file, the address of the loop is: 4015fc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X14, X3, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X11, X3, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4015f0 <main._omp_fn.5+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, 4014a4 <main._omp_fn.5+0x44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ANDS X6, X4, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X7, [X5, #1544]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X12, X13, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
B.EQ 401568 <main._omp_fn.5+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401550 <main._omp_fn.5+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401540 <main._omp_fn.5+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401530 <main._omp_fn.5+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401520 <main._omp_fn.5+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401510 <main._omp_fn.5+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401500 <main._omp_fn.5+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D21, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D0, D21, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D0, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D1, D20, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D1, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D2, D19, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D2, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D3, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D4, D17, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D4, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D5, D16, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D5, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D6, D7, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D6, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4015f0 <main._omp_fn.5+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 401494 <main._omp_fn.5+0x34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.5
Source file and lines	stream.c:334-336
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:334-336.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.38 to 5.17 cycles (1.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7 FP arithmetical operations:

7: multiply

The binary loop is loading 120 bytes. The binary loop is storing 56 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	59
nb uops	59
loop length	236
used w registers	0
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	15
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.38 cycles
front end	7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	3.50	3.50	6.50	6.17	6.33	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	3.50	3.50	6.50	6.17	6.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.38
Dispatch	6.50
Overall L1	7.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	27%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	27%
store	25%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.38 cycles. At this rate:

16% of peak load performance is reached (16.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.59 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4015fc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X14, X3, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X11, X3, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4015f0 <main._omp_fn.5+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, 4014a4 <main._omp_fn.5+0x44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ANDS X6, X4, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X7, [X5, #1544]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X12, X13, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
B.EQ 401568 <main._omp_fn.5+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401550 <main._omp_fn.5+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401540 <main._omp_fn.5+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401530 <main._omp_fn.5+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401520 <main._omp_fn.5+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401510 <main._omp_fn.5+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401500 <main._omp_fn.5+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D21, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D0, D21, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D0, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D1, D20, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D1, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D2, D19, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D2, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D3, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D4, D17, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D4, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D5, D16, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D5, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D6, D7, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D6, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4015f0 <main._omp_fn.5+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 401494 <main._omp_fn.5+0x34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code