OV - exec - Loop 4

	Loop Id: 4	Module: exec	Source: stream.c:358-360	Coverage: 0.00%

0x4010b4 MADD	X16, X3, X1, X0

0x4010b8 ADD	X12, X3, X16

0x4010bc CMP	X16, X12

0x4010c0 B.GE	401250

0x4010c4 ADRP	X4, 4010c4

0x4010c8 SUB	X5, X12, X16

0x4010cc LDR	D31, [X20]

0x4010d0 ANDS	X6, X5, #4224

0x4010d4 LDR	X7, [X4, #616]

0x4010d8 LDR	X15, [X7, #16]

0x4010dc LDP	X13, X14, [X7]

0x4010e0 B.EQ	4011a8

0x4010e4 CMP	X6, #1

0x4010e8 B.EQ	40118c

0x4010ec CMP	X6, #2

0x4010f0 B.EQ	401178

0x4010f4 CMP	X6, #3

0x4010f8 B.EQ	401164

0x4010fc CMP	X6, #4

0x401100 B.EQ	401150

0x401104 CMP	X6, #5

0x401108 B.EQ	40113c

0x40110c CMP	X6, #6

0x401110 B.EQ	401128

0x401114 LDR	D4, [X14, X16,LSL #3]

0x401118 LDR	D3, [X13, X16,LSL #3]

0x40111c FMADD	D0, D31, D4, D3

0x401120 STR	D0, [X15, X16,LSL #3]

0x401124 ADD	X16, X16, #1

0x401128 LDR	D2, [X14, X16,LSL #3]

0x40112c LDR	D1, [X13, X16,LSL #3]

0x401130 FMADD	D5, D31, D2, D1

0x401134 STR	D5, [X15, X16,LSL #3]

0x401138 ADD	X16, X16, #1

0x40113c LDR	D6, [X14, X16,LSL #3]

0x401140 LDR	D29, [X13, X16,LSL #3]

0x401144 FMADD	D7, D31, D6, D29

0x401148 STR	D7, [X15, X16,LSL #3]

0x40114c ADD	X16, X16, #1

0x401150 LDR	D30, [X14, X16,LSL #3]

0x401154 LDR	D28, [X13, X16,LSL #3]

0x401158 FMADD	D16, D31, D30, D28

0x40115c STR	D16, [X15, X16,LSL #3]

0x401160 ADD	X16, X16, #1

0x401164 LDR	D27, [X14, X16,LSL #3]

0x401168 LDR	D26, [X13, X16,LSL #3]

0x40116c FMADD	D17, D31, D27, D26

0x401170 STR	D17, [X15, X16,LSL #3]

0x401174 ADD	X16, X16, #1

0x401178 LDR	D25, [X14, X16,LSL #3]

0x40117c LDR	D24, [X13, X16,LSL #3]

0x401180 FMADD	D18, D31, D25, D24

0x401184 STR	D18, [X15, X16,LSL #3]

0x401188 ADD	X16, X16, #1

0x40118c LDR	D23, [X14, X16,LSL #3]

0x401190 LDR	D22, [X13, X16,LSL #3]

0x401194 FMADD	D19, D31, D23, D22

0x401198 STR	D19, [X15, X16,LSL #3]

0x40119c ADD	X16, X16, #1

0x4011a0 CMP	X12, X16

0x4011a4 B.EQ	401250

  (5) 0x4011a8 LDR	D21, [X14, X16,LSL #3]

  (5) 0x4011ac ADD	X17, X16, #1

  (5) 0x4011b0 ADD	X11, X16, #2

  (5) 0x4011b4 ADD	X10, X16, #3

  (5) 0x4011b8 ADD	X9, X16, #4

  (5) 0x4011bc LDR	D20, [X13, X16,LSL #3]

  (5) 0x4011c0 ADD	X8, X16, #5

  (5) 0x4011c4 ADD	X18, X16, #6

  (5) 0x4011c8 ADD	X30, X16, #7

  (5) 0x4011cc FMADD	D4, D31, D21, D20

  (5) 0x4011d0 STR	D4, [X15, X16,LSL #3]

  (5) 0x4011d4 ADD	X16, X16, #8

  (5) 0x4011d8 LDR	D3, [X14, X17,LSL #3]

  (5) 0x4011dc LDR	D0, [X13, X17,LSL #3]

  (5) 0x4011e0 FMADD	D2, D31, D3, D0

  (5) 0x4011e4 STR	D2, [X15, X17,LSL #3]

  (5) 0x4011e8 LDR	D1, [X14, X11,LSL #3]

  (5) 0x4011ec LDR	D5, [X13, X11,LSL #3]

  (5) 0x4011f0 FMADD	D6, D31, D1, D5

  (5) 0x4011f4 STR	D6, [X15, X11,LSL #3]

  (5) 0x4011f8 LDR	D29, [X14, X10,LSL #3]

  (5) 0x4011fc LDR	D7, [X13, X10,LSL #3]

  (5) 0x401200 FMADD	D30, D31, D29, D7

  (5) 0x401204 STR	D30, [X15, X10,LSL #3]

  (5) 0x401208 LDR	D28, [X14, X9,LSL #3]

  (5) 0x40120c LDR	D16, [X13, X9,LSL #3]

  (5) 0x401210 FMADD	D27, D31, D28, D16

  (5) 0x401214 STR	D27, [X15, X9,LSL #3]

  (5) 0x401218 LDR	D26, [X14, X8,LSL #3]

  (5) 0x40121c LDR	D17, [X13, X8,LSL #3]

  (5) 0x401220 FMADD	D25, D31, D26, D17

  (5) 0x401224 STR	D25, [X15, X8,LSL #3]

  (5) 0x401228 LDR	D24, [X14, X18,LSL #3]

  (5) 0x40122c LDR	D18, [X13, X18,LSL #3]

  (5) 0x401230 FMADD	D23, D31, D24, D18

  (5) 0x401234 STR	D23, [X15, X18,LSL #3]

  (5) 0x401238 LDR	D22, [X14, X30,LSL #3]

  (5) 0x40123c LDR	D19, [X13, X30,LSL #3]

  (5) 0x401240 FMADD	D21, D31, D22, D19

  (5) 0x401244 STR	D21, [X15, X30,LSL #3]

  (5) 0x401248 CMP	X12, X16

  (5) 0x40124c B.NE	4011a8

0x401250 LDP	X19, X20, [SP, #16]

0x401254 LDP	X29, X30, [SP], #32

0x401258 RET

0x40125c ADD	X3, X3, #1

0x401260 MOVZ	X0, #0

0x401264 B	4010b4

/home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c: 358 - 360

--------------------------------------------------------------------------------

358: #pragma omp parallel for

359: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

360: 	    a[j] = b[j]+scalar*c[j];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.22
CQA speedup if FP arith vectorized	1.13
CQA speedup if fully vectorized	3.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	main._omp_fn.7
Source	stream.c:358-360
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.17
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	8.08
CQA cycles if fully vectorized	2.38
Front-end cycles	8.38
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	5.50
P3 cycles	5.50
P4 cycles	5.50
P5 cycles	5.50
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	9.17
P11 cycles	8.83
P12 cycles	9.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	67.00
Nb uops	67.00
Nb loads	NA
Nb stores	7.00
Nb stack references	2.00
FLOP/cycle	1.53
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.18
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.60
Vector-efficiency ratio load	26.56
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.22
CQA speedup if FP arith vectorized	1.13
CQA speedup if fully vectorized	3.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	main._omp_fn.7
Source	stream.c:358-360
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.17
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	8.08
CQA cycles if fully vectorized	2.38
Front-end cycles	8.38
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	5.50
P3 cycles	5.50
P4 cycles	5.50
P5 cycles	5.50
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	9.17
P11 cycles	8.83
P12 cycles	9.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	67.00
Nb uops	67.00
Nb loads	NA
Nb stores	7.00
Nb stack references	2.00
FLOP/cycle	1.53
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.18
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.60
Vector-efficiency ratio load	26.56
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.7
Source file and lines	stream.c:358-360
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:358-360.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.17 to 7.50 cycles (1.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.17 to 2.37 cycles (3.86x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 7 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 184 bytes. The binary loop is storing 56 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	67
nb uops	67
loop length	268
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	22
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	3.50	3.50	9.17	8.83	9.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	3.50	3.50	9.17	8.83	9.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.38
Dispatch	9.17
Overall L1	9.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	26%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	26%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.17 cycles. At this rate:

20% of peak load performance is reached (20.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40125c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X16, X3, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X12, X3, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 401250 <main._omp_fn.7+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X4, 4010c4 <main._omp_fn.7+0x44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ANDS X6, X5, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X7, [X4, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X15, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X13, X14, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
B.EQ 4011a8 <main._omp_fn.7+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40118c <main._omp_fn.7+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401178 <main._omp_fn.7+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401164 <main._omp_fn.7+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401150 <main._omp_fn.7+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40113c <main._omp_fn.7+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401128 <main._omp_fn.7+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D3, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D0, D31, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D0, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D1, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D5, D31, D2, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D5, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D29, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D7, D31, D6, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D7, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D28, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D16, D31, D30, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D16, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D26, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D17, D31, D27, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D17, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D24, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D18, D31, D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D18, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D22, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D19, D31, D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D19, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401250 <main._omp_fn.7+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4010b4 <main._omp_fn.7+0x34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.7
Source file and lines	stream.c:358-360
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:358-360.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.17 to 7.50 cycles (1.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 7 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 184 bytes. The binary loop is storing 56 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	67
nb uops	67
loop length	268
used w registers	0
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	22
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	3.50	3.50	9.17	8.83	9.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	3.50	3.50	9.17	8.83	9.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.38
Dispatch	9.17
Overall L1	9.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	25%
load	26%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	25%
load	26%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.17 cycles. At this rate:

20% of peak load performance is reached (20.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40125c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X16, X3, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X12, X3, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 401250 <main._omp_fn.7+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X4, 4010c4 <main._omp_fn.7+0x44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ANDS X6, X5, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X7, [X4, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X15, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X13, X14, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
B.EQ 4011a8 <main._omp_fn.7+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40118c <main._omp_fn.7+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401178 <main._omp_fn.7+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401164 <main._omp_fn.7+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401150 <main._omp_fn.7+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40113c <main._omp_fn.7+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401128 <main._omp_fn.7+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D3, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D0, D31, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D0, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D1, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D5, D31, D2, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D5, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D29, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D7, D31, D6, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D7, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D28, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D16, D31, D30, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D16, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D26, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D17, D31, D27, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D17, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D24, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D18, D31, D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D18, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D22, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMADD D19, D31, D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (25.0%)
STR D19, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401250 <main._omp_fn.7+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4010b4 <main._omp_fn.7+0x34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code