OV - exec - Loop 15

	Loop Id: 15	Module: exec	Source: stream.c:277-279	Coverage: 0.07%

0x40192c STR	D30, [X15, X16,LSL #3]    [3]

0x401930 ADD	X17, X16, #1

0x401934 ADD	X11, X16, #2

0x401938 STR	D31, [X13, X16,LSL #3]    [1]

0x40193c ADD	X10, X16, #3

0x401940 ADD	X9, X16, #4

0x401944 STR	XZR, [X14, X16,LSL #3]    [2]

0x401948 ADD	X8, X16, #5

0x40194c ADD	X18, X16, #6

0x401950 STR	D30, [X15, X17,LSL #3]    [3]

0x401954 ADD	X30, X16, #7

0x401958 ADD	X16, X16, #8

0x40195c STR	D31, [X13, X17,LSL #3]    [1]

0x401960 STR	XZR, [X14, X17,LSL #3]    [2]

0x401964 STR	D30, [X15, X11,LSL #3]    [3]

0x401968 STR	D31, [X13, X11,LSL #3]    [1]

0x40196c STR	XZR, [X14, X11,LSL #3]    [2]

0x401970 STR	D30, [X15, X10,LSL #3]    [3]

0x401974 STR	D31, [X13, X10,LSL #3]    [1]

0x401978 STR	XZR, [X14, X10,LSL #3]    [2]

0x40197c STR	D30, [X15, X9,LSL #3]    [3]

0x401980 STR	D31, [X13, X9,LSL #3]    [1]

0x401984 STR	XZR, [X14, X9,LSL #3]    [2]

0x401988 STR	D30, [X15, X8,LSL #3]    [3]

0x40198c STR	D31, [X13, X8,LSL #3]    [1]

0x401990 STR	XZR, [X14, X8,LSL #3]    [2]

0x401994 STR	D30, [X15, X18,LSL #3]    [3]

0x401998 STR	D31, [X13, X18,LSL #3]    [1]

0x40199c STR	XZR, [X14, X18,LSL #3]    [2]

0x4019a0 STR	D30, [X15, X30,LSL #3]    [3]

0x4019a4 STR	D31, [X13, X30,LSL #3]    [1]

0x4019a8 STR	XZR, [X14, X30,LSL #3]    [2]

0x4019ac CMP	X12, X16

0x4019b0 B.NE	40192c

/home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c: 277 - 279

--------------------------------------------------------------------------------

277: 	    a[j] = 1.0;

278: 	    b[j] = 2.0;

279: 	    c[j] = 0.0;

Coverage (%)	Name	Source Location	Module
►98.43+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6
►1.57+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	main	stream.c:282	exec
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	stream.c:290	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11,
Function	main._omp_fn.2
Source	stream.c:277-279
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	3.00
Front-end cycles	4.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.25
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	24.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	192.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11,
Function	main._omp_fn.2
Source	stream.c:277-279
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	3.00
Front-end cycles	4.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.25
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	12.00
P11 cycles	12.00
P12 cycles	0.00
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	24.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	192.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.2
Source file and lines	stream.c:277-279
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:277-279.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 8.00 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 3.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 192 bytes.

General properties

nb instructions	34
nb uops	34
loop length	136
used w registers	0
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	12.00	12.00	0.00	4.00	4.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	12.00	12.00	0.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40192c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P13	P14	Latency	Recip. throughput	Vectorization
STR D30, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
ADD X17, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR D31, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
ADD X10, X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
ADD X8, X16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR D30, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
ADD X30, X16, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR D31, [X13, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
CMP X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.NE 40192c <main._omp_fn.2+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.2
Source file and lines	stream.c:277-279
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:277-279.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 8.00 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 192 bytes.

General properties

nb instructions	34
nb uops	34
loop length	136
used w registers	0
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	12.00	12.00	0.00	4.00	4.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	12.00	12.00	0.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40192c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P13	P14	Latency	Recip. throughput	Vectorization
STR D30, [X15, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
ADD X17, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR D31, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
ADD X10, X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
ADD X8, X16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR D30, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
ADD X30, X16, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
STR D31, [X13, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR D30, [X15, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR D31, [X13, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	2	0.50	scal (25.0%)
STR XZR, [X14, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
CMP X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33	N/A
B.NE 40192c <main._omp_fn.2+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code