OV - exec - Loop 10

	Loop Id: 10	Module: exec	Source: stream.c:322-324	Coverage: 0.00%

0x401640 MADD	X14, X2, X0, X3

0x401644 ADD	X11, X2, X14

0x401648 CMP	X14, X11

0x40164c B.GE	40175c

0x401650 ADRP	X5, 401650

0x401654 SUB	X4, X11, X14

0x401658 LDR	X6, [X5, #1912]

0x40165c ANDS	X7, X4, #4224

0x401660 LDP	X12, X13, [X6, #8]

0x401664 B.EQ	4016f4

0x401668 CMP	X7, #1

0x40166c B.EQ	4016e0

0x401670 CMP	X7, #2

0x401674 B.EQ	4016d4

0x401678 CMP	X7, #3

0x40167c B.EQ	4016c8

0x401680 CMP	X7, #4

0x401684 B.EQ	4016bc

0x401688 CMP	X7, #5

0x40168c B.EQ	4016b0

0x401690 CMP	X7, #6

0x401694 B.EQ	4016a4

0x401698 LDR	D31, [X13, X14,LSL #3]

0x40169c STR	D31, [X12, X14,LSL #3]

0x4016a0 ADD	X14, X14, #1

0x4016a4 LDR	D0, [X13, X14,LSL #3]

0x4016a8 STR	D0, [X12, X14,LSL #3]

0x4016ac ADD	X14, X14, #1

0x4016b0 LDR	D1, [X13, X14,LSL #3]

0x4016b4 STR	D1, [X12, X14,LSL #3]

0x4016b8 ADD	X14, X14, #1

0x4016bc LDR	D2, [X13, X14,LSL #3]

0x4016c0 STR	D2, [X12, X14,LSL #3]

0x4016c4 ADD	X14, X14, #1

0x4016c8 LDR	D3, [X13, X14,LSL #3]

0x4016cc STR	D3, [X12, X14,LSL #3]

0x4016d0 ADD	X14, X14, #1

0x4016d4 LDR	D4, [X13, X14,LSL #3]

0x4016d8 STR	D4, [X12, X14,LSL #3]

0x4016dc ADD	X14, X14, #1

0x4016e0 LDR	D5, [X13, X14,LSL #3]

0x4016e4 STR	D5, [X12, X14,LSL #3]

0x4016e8 ADD	X14, X14, #1

0x4016ec CMP	X11, X14

0x4016f0 B.EQ	40175c

  (11) 0x4016f4 LDR	D6, [X13, X14,LSL #3]

  (11) 0x4016f8 ADD	X15, X14, #1

  (11) 0x4016fc ADD	X10, X14, #2

  (11) 0x401700 ADD	X9, X14, #3

  (11) 0x401704 ADD	X8, X14, #4

  (11) 0x401708 ADD	X16, X14, #5

  (11) 0x40170c ADD	X17, X14, #6

  (11) 0x401710 ADD	X18, X14, #7

  (11) 0x401714 STR	D6, [X12, X14,LSL #3]

  (11) 0x401718 ADD	X14, X14, #8

  (11) 0x40171c LDR	D7, [X13, X15,LSL #3]

  (11) 0x401720 STR	D7, [X12, X15,LSL #3]

  (11) 0x401724 LDR	D16, [X13, X10,LSL #3]

  (11) 0x401728 STR	D16, [X12, X10,LSL #3]

  (11) 0x40172c LDR	D17, [X13, X9,LSL #3]

  (11) 0x401730 STR	D17, [X12, X9,LSL #3]

  (11) 0x401734 LDR	D18, [X13, X8,LSL #3]

  (11) 0x401738 STR	D18, [X12, X8,LSL #3]

  (11) 0x40173c LDR	D19, [X13, X16,LSL #3]

  (11) 0x401740 STR	D19, [X12, X16,LSL #3]

  (11) 0x401744 LDR	D20, [X13, X17,LSL #3]

  (11) 0x401748 STR	D20, [X12, X17,LSL #3]

  (11) 0x40174c LDR	D21, [X13, X18,LSL #3]

  (11) 0x401750 STR	D21, [X12, X18,LSL #3]

  (11) 0x401754 CMP	X11, X14

  (11) 0x401758 B.NE	4016f4

0x40175c LDR	X19, [SP, #16]

0x401760 LDP	X29, X30, [SP], #32

0x401764 RET

0x401768 ADD	X2, X2, #1

0x40176c MOVZ	X3, #0

0x401770 B	401640

/home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c: 322 - 324

--------------------------------------------------------------------------------

322: #pragma omp parallel for

323: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

324: 	    c[j] = a[j];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.32
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.92
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	main._omp_fn.4
Source	stream.c:322-324
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.38
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	6.38
CQA cycles if fully vectorized	1.63
Front-end cycles	6.38
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	5.50
P3 cycles	5.50
P4 cycles	5.50
P5 cycles	5.50
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	6.17
P11 cycles	5.83
P12 cycles	6.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	51.00
Nb loads	NA
Nb stores	7.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.10
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.89
Vector-efficiency ratio load	27.78
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.32
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.92
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	main._omp_fn.4
Source	stream.c:322-324
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.38
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	6.38
CQA cycles if fully vectorized	1.63
Front-end cycles	6.38
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	5.50
P3 cycles	5.50
P4 cycles	5.50
P5 cycles	5.50
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	6.17
P11 cycles	5.83
P12 cycles	6.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	51.00
Nb loads	NA
Nb stores	7.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.10
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.89
Vector-efficiency ratio load	27.78
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.4
Source file and lines	stream.c:322-324
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:322-324.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.38 to 4.83 cycles (1.32x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.38 to 1.62 cycles (3.92x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	51
nb uops	51
loop length	204
used w registers	0
used x registers	14
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	0.00	0.00	6.17	5.83	6.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	0.00	0.00	6.17	5.83	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Dispatch	6.17
Overall L1	6.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	27%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.38 cycles. At this rate:

16% of peak load performance is reached (16.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 401768

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X14, X2, X0, X3	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X11, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40175c <main._omp_fn.4+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, 401650 <main._omp_fn.4+0x40>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X4, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X6, [X5, #1912]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ANDS X7, X4, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
LDP X12, X13, [X6, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
B.EQ 4016f4 <main._omp_fn.4+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016e0 <main._omp_fn.4+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016d4 <main._omp_fn.4+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016c8 <main._omp_fn.4+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016bc <main._omp_fn.4+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016b0 <main._omp_fn.4+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016a4 <main._omp_fn.4+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D31, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D0, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D0, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D1, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D1, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D2, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D2, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D3, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D3, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D4, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D4, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D5, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D5, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40175c <main._omp_fn.4+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B 401640 <main._omp_fn.4+0x30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.4
Source file and lines	stream.c:322-324
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:322-324.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.38 to 4.83 cycles (1.32x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	51
nb uops	51
loop length	204
used w registers	0
used x registers	14
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	0.00	0.00	6.17	5.83	6.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	3.50	3.50	0.00	0.00	6.17	5.83	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Dispatch	6.17
Overall L1	6.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	27%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.38 cycles. At this rate:

16% of peak load performance is reached (16.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 401768

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X14, X2, X0, X3	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X11, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40175c <main._omp_fn.4+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, 401650 <main._omp_fn.4+0x40>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X4, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X6, [X5, #1912]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ANDS X7, X4, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
LDP X12, X13, [X6, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
B.EQ 4016f4 <main._omp_fn.4+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016e0 <main._omp_fn.4+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016d4 <main._omp_fn.4+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016c8 <main._omp_fn.4+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016bc <main._omp_fn.4+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016b0 <main._omp_fn.4+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016a4 <main._omp_fn.4+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D31, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D0, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D0, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D1, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D1, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D2, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D2, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D3, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D3, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D4, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D4, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR D5, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D5, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40175c <main._omp_fn.4+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B 401640 <main._omp_fn.4+0x30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code