OV - exec - Loop 2

0x401380 STUR	X11, [X10, #496]    [2]

0x401384 STUR	X12, [X9, #496]    [1]

0x401388 SUBS	X8, X8, #4

0x40138c STUR	X11, [X10, #504]    [2]

0x401390 STUR	X12, [X9, #504]    [1]

0x401394 STR	X11, [X10]    [2]

0x401398 STR	X12, [X9]    [1]

0x40139c STR	X11, [X10, #8]    [2]

0x4013a0 ADD	X10, X10, #32

0x4013a4 STR	X12, [X9, #8]    [1]

0x4013a8 ADD	X9, X9, #32

0x4013ac B.NE	401380

/home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c: 276 - 278

--------------------------------------------------------------------------------

276:     for (j=0; j<STREAM_ARRAY_SIZE; j++) {

277: 	    a[j] = 1.0;

278: 	    b[j] = 2.0;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks	P10, P11, P13, P14,
Function	main.omp_outlined.14
Source	stream.c:276-278
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.00
Front-end cycles	1.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	12.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks	P10, P11, P13, P14,
Function	main.omp_outlined.14
Source	stream.c:276-278
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.00
Front-end cycles	1.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	12.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main.omp_outlined.14
Source file and lines	stream.c:276-278
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:276-278.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

General properties

nb instructions	12
nb uops	12
loop length	48
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.50
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput	Vectorization
STUR X11, [X10, #496]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STUR X12, [X9, #496]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
SUBS X8, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (25.0%)
STUR X11, [X10, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STUR X12, [X9, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [X10]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [X9]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [X10, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
ADD X10, X10, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STR X12, [X9, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X9, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
B.NE 401380 <main.omp_outlined.14+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main.omp_outlined.14
Source file and lines	stream.c:276-278
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:276-278.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

General properties

nb instructions	12
nb uops	12
loop length	48
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.50
Dispatch	4.00
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 401380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput	Vectorization
STUR X11, [X10, #496]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STUR X12, [X9, #496]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
SUBS X8, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (25.0%)
STUR X11, [X10, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STUR X12, [X9, #504]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [X10]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [X9]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [X10, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
ADD X10, X10, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
STR X12, [X9, #8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X9, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
B.NE 401380 <main.omp_outlined.14+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code