OV - exec - Loop 7

	Loop Id: 7	Module: exec	Source: stream.c:346-348	Coverage: 0.00%

0x401510 MADD	X1, X5, X1, X0

0x401514 ADD	X12, X5, X1

0x401518 CMP	X1, X12

0x40151c B.GE	40170c

0x401520 ADRP	X3, 401520

0x401524 LDR	X4, [X3, #2208]

0x401528 LDR	X8, [X4, #16]

0x40152c LDP	X9, X10, [X4]

0x401530 CMP	X5, #1

0x401534 B.EQ	401724

0x401538 UBFM	X11, X1, #61, #60

0x40153c ADD	X17, X10, X1,LSL #3

0x401540 ADD	X7, X11, #8

0x401544 ADD	X6, X8, X7

0x401548 ADD	X13, X9, X7

0x40154c CMP	X6, X17

0x401550 CCMP	X13, X17, #4, #1

0x401554 B.EQ	401724

0x401558 UBFM	X14, X5, #1, #63

0x40155c ADD	X18, X8, X11

0x401560 UBFM	X30, X14, #60, #59

0x401564 MOVZ	X0, #0

0x401568 SUB	X15, X30, #16

0x40156c ADD	X19, X9, X11

0x401570 UBFM	X16, X15, #4, #63

0x401574 ADD	X2, X16, #1

0x401578 ANDS	X12, X2, #4224

0x40157c B.EQ	401644

0x401580 CMP	X12, #1

0x401584 B.EQ	401628

0x401588 CMP	X12, #2

0x40158c B.EQ	401614

0x401590 CMP	X12, #3

0x401594 B.EQ	401600

0x401598 CMP	X12, #4

0x40159c B.EQ	4015ec

0x4015a0 CMP	X12, #5

0x4015a4 B.EQ	4015d8

0x4015a8 CMP	X12, #6

0x4015ac B.EQ	4015c4

0x4015b0 LDR	Q30, [X19]

0x4015b4 MOVZ	X0, #16

0x4015b8 LDR	Q31, [X18]

0x4015bc FADD	V0.2D, V31.2D, V30.2D

0x4015c0 STR	Q0, [X17]

0x4015c4 LDR	Q29, [X18, X0]

0x4015c8 LDR	Q28, [X19, X0]

0x4015cc FADD	V1.2D, V29.2D, V28.2D

0x4015d0 STR	Q1, [X17, X0]

0x4015d4 ADD	X0, X0, #16

0x4015d8 LDR	Q27, [X18, X0]

0x4015dc LDR	Q26, [X19, X0]

0x4015e0 FADD	V2.2D, V27.2D, V26.2D

0x4015e4 STR	Q2, [X17, X0]

0x4015e8 ADD	X0, X0, #16

0x4015ec LDR	Q25, [X18, X0]

0x4015f0 LDR	Q24, [X19, X0]

0x4015f4 FADD	V3.2D, V25.2D, V24.2D

0x4015f8 STR	Q3, [X17, X0]

0x4015fc ADD	X0, X0, #16

0x401600 LDR	Q23, [X18, X0]

0x401604 LDR	Q22, [X19, X0]

0x401608 FADD	V4.2D, V23.2D, V22.2D

0x40160c STR	Q4, [X17, X0]

0x401610 ADD	X0, X0, #16

0x401614 LDR	Q21, [X18, X0]

0x401618 LDR	Q20, [X19, X0]

0x40161c FADD	V5.2D, V21.2D, V20.2D

0x401620 STR	Q5, [X17, X0]

0x401624 ADD	X0, X0, #16

0x401628 LDR	Q19, [X18, X0]

0x40162c LDR	Q18, [X19, X0]

0x401630 FADD	V6.2D, V19.2D, V18.2D

0x401634 STR	Q6, [X17, X0]

0x401638 ADD	X0, X0, #16

0x40163c CMP	X30, X0

0x401640 B.EQ	4016ec

  (9) 0x401644 LDR	Q7, [X18, X0]

  (9) 0x401648 ADD	X3, X0, #16

  (9) 0x40164c ADD	X7, X0, #32

  (9) 0x401650 ADD	X4, X0, #48

  (9) 0x401654 ADD	X6, X0, #64

  (9) 0x401658 LDR	Q16, [X19, X0]

  (9) 0x40165c ADD	X13, X0, #80

  (9) 0x401660 ADD	X14, X0, #96

  (9) 0x401664 ADD	X11, X0, #112

  (9) 0x401668 FADD	V17.2D, V7.2D, V16.2D

  (9) 0x40166c STR	Q17, [X17, X0]

  (9) 0x401670 ADD	X0, X0, #128

  (9) 0x401674 LDR	Q30, [X18, X3]

  (9) 0x401678 LDR	Q31, [X19, X3]

  (9) 0x40167c FADD	V0.2D, V30.2D, V31.2D

  (9) 0x401680 STR	Q0, [X17, X3]

  (9) 0x401684 LDR	Q29, [X18, X7]

  (9) 0x401688 LDR	Q28, [X19, X7]

  (9) 0x40168c FADD	V1.2D, V29.2D, V28.2D

  (9) 0x401690 STR	Q1, [X17, X7]

  (9) 0x401694 LDR	Q27, [X18, X4]

  (9) 0x401698 LDR	Q26, [X19, X4]

  (9) 0x40169c FADD	V2.2D, V27.2D, V26.2D

  (9) 0x4016a0 STR	Q2, [X17, X4]

  (9) 0x4016a4 LDR	Q25, [X18, X6]

  (9) 0x4016a8 LDR	Q24, [X19, X6]

  (9) 0x4016ac FADD	V3.2D, V25.2D, V24.2D

  (9) 0x4016b0 STR	Q3, [X17, X6]

  (9) 0x4016b4 LDR	Q23, [X18, X13]

  (9) 0x4016b8 LDR	Q22, [X19, X13]

  (9) 0x4016bc FADD	V4.2D, V23.2D, V22.2D

  (9) 0x4016c0 STR	Q4, [X17, X13]

  (9) 0x4016c4 LDR	Q21, [X18, X14]

  (9) 0x4016c8 LDR	Q20, [X19, X14]

  (9) 0x4016cc FADD	V5.2D, V21.2D, V20.2D

  (9) 0x4016d0 STR	Q5, [X17, X14]

  (9) 0x4016d4 LDR	Q19, [X18, X11]

  (9) 0x4016d8 LDR	Q18, [X19, X11]

  (9) 0x4016dc FADD	V6.2D, V19.2D, V18.2D

  (9) 0x4016e0 STR	Q6, [X17, X11]

  (9) 0x4016e4 CMP	X30, X0

  (9) 0x4016e8 B.NE	401644

0x4016ec AND	X17, X5, #8127

0x4016f0 TBZ	W5, #0, 40170c

0x4016f4 ADD	X1, X1, X17

0x4016f8 UBFM	X5, X1, #61, #60

0x4016fc LDR	D7, [X8, X5]

0x401700 LDR	D16, [X9, X5]

0x401704 FADD	D17, D7, D16

0x401708 STR	D17, [X10, X5]

0x40170c LDR	X19, [SP, #16]

0x401710 LDP	X29, X30, [SP], #32

0x401714 RET

0x401718 ADD	X5, X5, #1

0x40171c MOVZ	X0, #0

0x401720 B	401510

0x401724 SUB	X18, X12, X1

0x401728 ANDS	X30, X18, #4224

0x40172c B.EQ	4017f4

0x401730 CMP	X30, #1

0x401734 B.EQ	4017d8

0x401738 CMP	X30, #2

0x40173c B.EQ	4017c4

0x401740 CMP	X30, #3

0x401744 B.EQ	4017b0

0x401748 CMP	X30, #4

0x40174c B.EQ	40179c

0x401750 CMP	X30, #5

0x401754 B.EQ	401788

0x401758 CMP	X30, #6

0x40175c B.EQ	401774

0x401760 LDR	D30, [X8, X1,LSL #3]

0x401764 LDR	D31, [X9, X1,LSL #3]

0x401768 FADD	D0, D30, D31

0x40176c STR	D0, [X10, X1,LSL #3]

0x401770 ADD	X1, X1, #1

0x401774 LDR	D29, [X8, X1,LSL #3]

0x401778 LDR	D28, [X9, X1,LSL #3]

0x40177c FADD	D1, D29, D28

0x401780 STR	D1, [X10, X1,LSL #3]

0x401784 ADD	X1, X1, #1

0x401788 LDR	D27, [X8, X1,LSL #3]

0x40178c LDR	D26, [X9, X1,LSL #3]

0x401790 FADD	D2, D27, D26

0x401794 STR	D2, [X10, X1,LSL #3]

0x401798 ADD	X1, X1, #1

0x40179c LDR	D25, [X8, X1,LSL #3]

0x4017a0 LDR	D24, [X9, X1,LSL #3]

0x4017a4 FADD	D3, D25, D24

0x4017a8 STR	D3, [X10, X1,LSL #3]

0x4017ac ADD	X1, X1, #1

0x4017b0 LDR	D23, [X8, X1,LSL #3]

0x4017b4 LDR	D22, [X9, X1,LSL #3]

0x4017b8 FADD	D4, D23, D22

0x4017bc STR	D4, [X10, X1,LSL #3]

0x4017c0 ADD	X1, X1, #1

0x4017c4 LDR	D21, [X8, X1,LSL #3]

0x4017c8 LDR	D20, [X9, X1,LSL #3]

0x4017cc FADD	D5, D21, D20

0x4017d0 STR	D5, [X10, X1,LSL #3]

0x4017d4 ADD	X1, X1, #1

0x4017d8 LDR	D19, [X8, X1,LSL #3]

0x4017dc LDR	D18, [X9, X1,LSL #3]

0x4017e0 FADD	D6, D19, D18

0x4017e4 STR	D6, [X10, X1,LSL #3]

0x4017e8 ADD	X1, X1, #1

0x4017ec CMP	X12, X1

0x4017f0 B.EQ	40170c

  (8) 0x4017f4 LDR	D7, [X8, X1,LSL #3]

  (8) 0x4017f8 ADD	X19, X1, #1

  (8) 0x4017fc ADD	X16, X1, #2

  (8) 0x401800 ADD	X15, X1, #3

  (8) 0x401804 ADD	X2, X1, #4

  (8) 0x401808 LDR	D16, [X9, X1,LSL #3]

  (8) 0x40180c ADD	X0, X1, #5

  (8) 0x401810 ADD	X4, X1, #6

  (8) 0x401814 ADD	X3, X1, #7

  (8) 0x401818 FADD	D17, D7, D16

  (8) 0x40181c STR	D17, [X10, X1,LSL #3]

  (8) 0x401820 ADD	X1, X1, #8

  (8) 0x401824 LDR	D30, [X8, X19,LSL #3]

  (8) 0x401828 LDR	D31, [X9, X19,LSL #3]

  (8) 0x40182c FADD	D0, D30, D31

  (8) 0x401830 STR	D0, [X10, X19,LSL #3]

  (8) 0x401834 LDR	D29, [X8, X16,LSL #3]

  (8) 0x401838 LDR	D28, [X9, X16,LSL #3]

  (8) 0x40183c FADD	D1, D29, D28

  (8) 0x401840 STR	D1, [X10, X16,LSL #3]

  (8) 0x401844 LDR	D27, [X8, X15,LSL #3]

  (8) 0x401848 LDR	D26, [X9, X15,LSL #3]

  (8) 0x40184c FADD	D2, D27, D26

  (8) 0x401850 STR	D2, [X10, X15,LSL #3]

  (8) 0x401854 LDR	D25, [X8, X2,LSL #3]

  (8) 0x401858 LDR	D24, [X9, X2,LSL #3]

  (8) 0x40185c FADD	D3, D25, D24

  (8) 0x401860 STR	D3, [X10, X2,LSL #3]

  (8) 0x401864 LDR	D23, [X8, X0,LSL #3]

  (8) 0x401868 LDR	D22, [X9, X0,LSL #3]

  (8) 0x40186c FADD	D4, D23, D22

  (8) 0x401870 STR	D4, [X10, X0,LSL #3]

  (8) 0x401874 LDR	D21, [X8, X4,LSL #3]

  (8) 0x401878 LDR	D20, [X9, X4,LSL #3]

  (8) 0x40187c FADD	D5, D21, D20

  (8) 0x401880 STR	D5, [X10, X4,LSL #3]

  (8) 0x401884 LDR	D19, [X8, X3,LSL #3]

  (8) 0x401888 LDR	D18, [X9, X3,LSL #3]

  (8) 0x40188c FADD	D6, D19, D18

  (8) 0x401890 STR	D6, [X10, X3,LSL #3]

  (8) 0x401894 CMP	X12, X1

  (8) 0x401898 B.NE	4017f4

0x40189c B	40170c

/home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c: 346 - 348

--------------------------------------------------------------------------------

346: #pragma omp parallel for

347: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

348: 	    c[j] = a[j]+b[j];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.19
CQA speedup if FP arith vectorized	1.14
CQA speedup if fully vectorized	3.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	main._omp_fn.6
Source	stream.c:346-348
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00
CQA cycles if no scalar integer	15.17
CQA cycles if FP arith vectorized	15.75
CQA cycles if fully vectorized	6.00
Front-end cycles	18.00
P0 cycles	11.50
P1 cycles	11.50
P2 cycles	14.00
P3 cycles	14.00
P4 cycles	14.00
P5 cycles	14.00
P6 cycles	7.50
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	16.83
P11 cycles	16.50
P12 cycles	16.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	144.00
Nb uops	144.00
Nb loads	NA
Nb stores	15.00
Nb stack references	2.00
FLOP/cycle	1.22
Nb FLOP add-sub	22.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.44
Bytes prefetched	0.00
Bytes loaded	408.00
Bytes stored	176.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	31.82
Vectorization ratio load	45.16
Vectorization ratio store	46.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	35.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	33.24
Vector-efficiency ratio load	37.10
Vector-efficiency ratio store	36.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	33.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.19
CQA speedup if FP arith vectorized	1.14
CQA speedup if fully vectorized	3.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	main._omp_fn.6
Source	stream.c:346-348
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00
CQA cycles if no scalar integer	15.17
CQA cycles if FP arith vectorized	15.75
CQA cycles if fully vectorized	6.00
Front-end cycles	18.00
P0 cycles	11.50
P1 cycles	11.50
P2 cycles	14.00
P3 cycles	14.00
P4 cycles	14.00
P5 cycles	14.00
P6 cycles	7.50
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	16.83
P11 cycles	16.50
P12 cycles	16.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	144.00
Nb uops	144.00
Nb loads	NA
Nb stores	15.00
Nb stack references	2.00
FLOP/cycle	1.22
Nb FLOP add-sub	22.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.44
Bytes prefetched	0.00
Bytes loaded	408.00
Bytes stored	176.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	31.82
Vectorization ratio load	45.16
Vectorization ratio store	46.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	35.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	33.24
Vector-efficiency ratio load	37.10
Vector-efficiency ratio store	36.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	33.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.6
Source file and lines	stream.c:346-348
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:346-348.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.00 to 15.17 cycles (1.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 33% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 18.00 to 6.00 cycles (3.00x speedup).

Details

31% of VPU instructions are used in vector version (process two or more data elements in vector registers):

45% of VPU loads are used in vector version.
46% of VPU stores are used in vector version.
35% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 22 FP arithmetical operations:

22: addition or subtraction

The binary loop is loading 408 bytes. The binary loop is storing 176 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	144
nb uops	144
loop length	576
used w registers	1
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	24
used q registers	21
used v registers	21
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	14.00	14.00	14.00	14.00	7.50	7.50	7.50	7.50	16.83	16.50	16.67	0.00	0.00
cycles	11.50	11.50	14.00	14.00	14.00	14.00	7.50	7.50	7.50	7.50	16.83	16.50	16.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.00
Dispatch	16.83
Overall L1	18.00

Vectorization ratios

INT

all	28%
load	45%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	46%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	31%
load	45%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	35%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	32%
load	37%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	36%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	36%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	37%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

23% of peak load performance is reached (22.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.00 to 16.83 cycles (1.07x speedup).

ASM code

In the binary file, the address of the loop is: 401718

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X1, X5, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X12, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40170c <main._omp_fn.6+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, 401520 <main._omp_fn.6+0x40>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X3, #2208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X8, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X9, X10, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401724 <main._omp_fn.6+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X11, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X10, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X8, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X13, X17, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.EQ 401724 <main._omp_fn.6+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X14, X5, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X30, X14, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X15, X30, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X15, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X12, X2, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401644 <main._omp_fn.6+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401628 <main._omp_fn.6+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401614 <main._omp_fn.6+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401600 <main._omp_fn.6+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4015ec <main._omp_fn.6+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4015d8 <main._omp_fn.6+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4015c4 <main._omp_fn.6+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q31, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V0.2D, V31.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q0, [X17]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q29, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q28, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V1.2D, V29.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q1, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q27, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q26, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V2.2D, V27.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q2, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q25, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q24, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V3.2D, V25.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q3, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q23, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q22, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V4.2D, V23.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q4, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q21, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q20, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V5.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q5, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q19, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q18, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V6.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q6, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016ec <main._omp_fn.6+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X17, X5, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W5, #0, 40170c <main._omp_fn.6+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X5, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X8, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D16, [X9, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D17, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D17, [X10, X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 401510 <main._omp_fn.6+0x30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X18, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X30, X18, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4017f4 <main._omp_fn.6+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4017d8 <main._omp_fn.6+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4017c4 <main._omp_fn.6+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4017b0 <main._omp_fn.6+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40179c <main._omp_fn.6+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401788 <main._omp_fn.6+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401774 <main._omp_fn.6+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D30, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D31, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D0, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D0, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D29, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D28, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D1, D29, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D1, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D26, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D2, D27, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D2, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D24, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D3, D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D3, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D22, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D4, D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D4, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D20, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D5, D21, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D5, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D18, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D6, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D6, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 40170c <main._omp_fn.6+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 40170c <main._omp_fn.6+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.6
Source file and lines	stream.c:346-348
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:346-348.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

31% of VPU instructions are used in vector version (process two or more data elements in vector registers):

45% of VPU loads are used in vector version.
46% of VPU stores are used in vector version.
35% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 22 FP arithmetical operations:

22: addition or subtraction

The binary loop is loading 408 bytes. The binary loop is storing 176 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	144
nb uops	144
loop length	576
used w registers	1
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	24
used q registers	21
used v registers	21
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	14.00	14.00	14.00	14.00	7.50	7.50	7.50	7.50	16.83	16.50	16.67	0.00	0.00
cycles	11.50	11.50	14.00	14.00	14.00	14.00	7.50	7.50	7.50	7.50	16.83	16.50	16.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.00
Dispatch	16.83
Overall L1	18.00

Vectorization ratios

INT

all	28%
load	45%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	46%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	31%
load	45%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	35%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	32%
load	37%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	36%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	36%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	37%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

23% of peak load performance is reached (22.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 401718

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X1, X5, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X12, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40170c <main._omp_fn.6+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, 401520 <main._omp_fn.6+0x40>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X3, #2208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X8, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X9, X10, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401724 <main._omp_fn.6+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X11, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X10, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X8, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X13, X17, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.EQ 401724 <main._omp_fn.6+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X14, X5, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X30, X14, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X15, X30, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X15, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X12, X2, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401644 <main._omp_fn.6+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401628 <main._omp_fn.6+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401614 <main._omp_fn.6+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401600 <main._omp_fn.6+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4015ec <main._omp_fn.6+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4015d8 <main._omp_fn.6+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4015c4 <main._omp_fn.6+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q31, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V0.2D, V31.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q0, [X17]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q29, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q28, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V1.2D, V29.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q1, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q27, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q26, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V2.2D, V27.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q2, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q25, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q24, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V3.2D, V25.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q3, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q23, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q22, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V4.2D, V23.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q4, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q21, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q20, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V5.2D, V21.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q5, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q19, [X18, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q18, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FADD V6.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STR Q6, [X17, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4016ec <main._omp_fn.6+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X17, X5, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W5, #0, 40170c <main._omp_fn.6+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X5, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X8, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D16, [X9, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D17, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D17, [X10, X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 401510 <main._omp_fn.6+0x30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X18, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X30, X18, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4017f4 <main._omp_fn.6+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4017d8 <main._omp_fn.6+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4017c4 <main._omp_fn.6+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4017b0 <main._omp_fn.6+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40179c <main._omp_fn.6+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401788 <main._omp_fn.6+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401774 <main._omp_fn.6+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D30, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D31, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D0, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D0, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D29, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D28, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D1, D29, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D1, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D26, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D2, D27, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D2, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D25, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D24, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D3, D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D3, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D22, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D4, D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D4, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D20, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D5, D21, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D5, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D18, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD D6, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
STR D6, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 40170c <main._omp_fn.6+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 40170c <main._omp_fn.6+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code