OV - exec - Loop 18

	Loop Id: 18	Module: exec	Source: stream.c:296-296	Coverage: 0.19%

0x4021ac LDP	Q28, Q29, [X30]    [2]

0x4021b0 ORR	X18, XZR, X30

0x4021b4 LDP	Q26, Q27, [X30, #32]    [2]

0x4021b8 LDP	Q24, Q25, [X30, #64]    [2]

0x4021bc LDP	Q22, Q23, [X30, #96]    [2]

0x4021c0 LDP	Q20, Q21, [X30, #128]    [2]

0x4021c4 FADD	V2.2D, V28.2D, V28.2D

0x4021c8 LDP	Q4, Q5, [X30, #160]    [2]

0x4021cc FADD	V3.2D, V29.2D, V29.2D

0x4021d0 LDP	Q6, Q7, [X30, #192]    [2]

0x4021d4 FADD	V18.2D, V26.2D, V26.2D

0x4021d8 LDP	Q16, Q17, [X30, #224]    [2]

0x4021dc ADD	X30, X30, #256

0x4021e0 FADD	V19.2D, V27.2D, V27.2D

0x4021e4 FADD	V30.2D, V24.2D, V24.2D

0x4021e8 FADD	V31.2D, V25.2D, V25.2D

0x4021ec FADD	V0.2D, V22.2D, V22.2D

0x4021f0 FADD	V1.2D, V23.2D, V23.2D

0x4021f4 FADD	V28.2D, V20.2D, V20.2D

0x4021f8 FADD	V29.2D, V21.2D, V21.2D

0x4021fc FADD	V26.2D, V6.2D, V6.2D

0x402200 FADD	V27.2D, V7.2D, V7.2D

0x402204 FADD	V24.2D, V16.2D, V16.2D

0x402208 STP	Q2, Q3, [X30, #1792]    [1]

0x40220c FADD	V2.2D, V4.2D, V4.2D

0x402210 FADD	V3.2D, V5.2D, V5.2D

0x402214 FADD	V25.2D, V17.2D, V17.2D

0x402218 STP	Q18, Q19, [X30, #1824]    [1]

0x40221c STP	Q30, Q31, [X30, #1856]    [1]

0x402220 STP	Q0, Q1, [X30, #1888]    [1]

0x402224 STP	Q28, Q29, [X30, #1920]    [1]

0x402228 STP	Q2, Q3, [X30, #1952]    [1]

0x40222c STP	Q26, Q27, [X30, #1984]    [1]

0x402230 STUR	Q24, [X30, #480]    [1]

0x402234 STR	Q25, [X18, #240]    [3]

0x402238 CMP	X30, X14

0x40223c B.NE	4021ac

/home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c: 296 - 296

--------------------------------------------------------------------------------

296: 		a[j] = 2.0E0 * a[j];

Coverage (%)	Name	Source Location	Module
►98.35+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6
►1.65+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	main	stream.c:445	exec
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	stream.c:290	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.85
CQA speedup if fully vectorized	1.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P6, P7, P8, P9,
Function	main._omp_fn.3
Source	stream.c:296-296
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.25
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	5.33
Front-end cycles	4.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	5.83
P11 cycles	5.50
P12 cycles	5.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	5.12
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	81.92
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	72.73
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	88.89
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.85
CQA speedup if fully vectorized	1.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P6, P7, P8, P9,
Function	main._omp_fn.3
Source	stream.c:296-296
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.25
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	5.33
Front-end cycles	4.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.75
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	5.83
P11 cycles	5.50
P12 cycles	5.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	5.12
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	81.92
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	72.73
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	88.89
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.3
Source file and lines	stream.c:296-296
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:296.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 72% register length (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.25 to 5.33 cycles (1.17x speedup).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: addition or subtraction

The binary loop is loading 256 bytes. The binary loop is storing 256 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	37
nb uops	37
loop length	148
used w registers	0
used x registers	4
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	24
used v registers	24
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	6.25	6.25	6.25	6.25	5.83	5.50	5.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	6.25	6.25	6.25	6.25	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Dispatch	6.25
Data deps.	1.00
Overall L1	6.25

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	94%
load	100%
store	88%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	72%
load	100%
store	88%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

42% of peak load performance is reached (40.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
85% of peak store performance is reached (40.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4021ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDP Q28, Q29, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR X18, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q26, Q27, [X30, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q24, Q25, [X30, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q22, Q23, [X30, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q20, Q21, [X30, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V2.2D, V28.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDP Q4, Q5, [X30, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V3.2D, V29.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDP Q6, Q7, [X30, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V18.2D, V26.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDP Q16, Q17, [X30, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X30, X30, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V19.2D, V27.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V30.2D, V24.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V31.2D, V25.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V0.2D, V22.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V1.2D, V23.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V28.2D, V20.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V29.2D, V21.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V26.2D, V6.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V27.2D, V7.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V24.2D, V16.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STP Q2, Q3, [X30, #1792]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
FADD V2.2D, V4.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V3.2D, V5.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V25.2D, V17.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STP Q18, Q19, [X30, #1824]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q30, Q31, [X30, #1856]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q0, Q1, [X30, #1888]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q28, Q29, [X30, #1920]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q2, Q3, [X30, #1952]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q26, Q27, [X30, #1984]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STUR Q24, [X30, #480]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q25, [X18, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
CMP X30, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 4021ac <main._omp_fn.3+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.3
Source file and lines	stream.c:296-296
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:296.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

32: addition or subtraction

The binary loop is loading 256 bytes. The binary loop is storing 256 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	37
nb uops	37
loop length	148
used w registers	0
used x registers	4
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	24
used v registers	24
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	6.25	6.25	6.25	6.25	5.83	5.50	5.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	6.25	6.25	6.25	6.25	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Dispatch	6.25
Data deps.	1.00
Overall L1	6.25

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	94%
load	100%
store	88%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	72%
load	100%
store	88%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

42% of peak load performance is reached (40.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
85% of peak store performance is reached (40.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4021ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDP Q28, Q29, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR X18, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDP Q26, Q27, [X30, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q24, Q25, [X30, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q22, Q23, [X30, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q20, Q21, [X30, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V2.2D, V28.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDP Q4, Q5, [X30, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V3.2D, V29.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDP Q6, Q7, [X30, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V18.2D, V26.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDP Q16, Q17, [X30, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X30, X30, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V19.2D, V27.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V30.2D, V24.2D, V24.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V31.2D, V25.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V0.2D, V22.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V1.2D, V23.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V28.2D, V20.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V29.2D, V21.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V26.2D, V6.2D, V6.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V27.2D, V7.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V24.2D, V16.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STP Q2, Q3, [X30, #1792]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
FADD V2.2D, V4.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V3.2D, V5.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FADD V25.2D, V17.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
STP Q18, Q19, [X30, #1824]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q30, Q31, [X30, #1856]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q0, Q1, [X30, #1888]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q28, Q29, [X30, #1920]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q2, Q3, [X30, #1952]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q26, Q27, [X30, #1984]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STUR Q24, [X30, #480]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q25, [X18, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
CMP X30, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 4021ac <main._omp_fn.3+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code