OV - exec - Loop 13

	Loop Id: 13	Module: exec	Source: stream.c:322-324	Coverage: 0.00%

0x401d30 MADD	X0, X4, X0, X2

0x401d34 ADD	X5, X4, X0

0x401d38 CMP	X0, X5

0x401d3c B.GE	401f2c

0x401d40 ADRP	X3, 402d40

0x401d44 UBFM	X6, X0, #61, #60

0x401d48 LDR	X7, [X3, #128]

0x401d4c ADD	X10, X6, #8

0x401d50 LDP	X8, X9, [X7, #8]

0x401d54 ADD	X17, X8, X0,LSL #3

0x401d58 ADD	X11, X9, X10

0x401d5c SUB	X12, X17, X11

0x401d60 CMP	X12, #16

0x401d64 B.LS	401f58

0x401d68 SUB	X13, X4, #1

0x401d6c CMP	X13, #2

0x401d70 B.LS	402074

0x401d74 UBFM	X15, X4, #2, #63

0x401d78 ADD	X18, X9, X6

0x401d7c UBFM	X30, X15, #59, #58

0x401d80 MOVZ	X1, #0

0x401d84 SUB	X16, X30, #32

0x401d88 ADD	X19, X18, #16

0x401d8c UBFM	X5, X16, #5, #63

0x401d90 ADD	X2, X17, #16

0x401d94 ADD	X3, X5, #1

0x401d98 ANDS	X6, X3, #4224

0x401d9c B.EQ	401e50

0x401da0 CMP	X6, #1

0x401da4 B.EQ	401e34

0x401da8 CMP	X6, #2

0x401dac B.EQ	401e20

0x401db0 CMP	X6, #3

0x401db4 B.EQ	401e0c

0x401db8 CMP	X6, #4

0x401dbc B.EQ	401df8

0x401dc0 CMP	X6, #5

0x401dc4 B.EQ	401de4

0x401dc8 CMP	X6, #6

0x401dcc B.NE	40205c

0x401dd0 LDR	Q0, [X18, X1]

0x401dd4 LDR	Q1, [X19, X1]

0x401dd8 STR	Q0, [X17, X1]

0x401ddc STR	Q1, [X2, X1]

0x401de0 ADD	X1, X1, #32

0x401de4 LDR	Q2, [X18, X1]

0x401de8 LDR	Q3, [X19, X1]

0x401dec STR	Q2, [X17, X1]

0x401df0 STR	Q3, [X2, X1]

0x401df4 ADD	X1, X1, #32

0x401df8 LDR	Q4, [X18, X1]

0x401dfc LDR	Q5, [X19, X1]

0x401e00 STR	Q4, [X17, X1]

0x401e04 STR	Q5, [X2, X1]

0x401e08 ADD	X1, X1, #32

0x401e0c LDR	Q6, [X18, X1]

0x401e10 LDR	Q7, [X19, X1]

0x401e14 STR	Q6, [X17, X1]

0x401e18 STR	Q7, [X2, X1]

0x401e1c ADD	X1, X1, #32

0x401e20 LDR	Q16, [X18, X1]

0x401e24 LDR	Q17, [X19, X1]

0x401e28 STR	Q16, [X17, X1]

0x401e2c STR	Q17, [X2, X1]

0x401e30 ADD	X1, X1, #32

0x401e34 LDR	Q18, [X18, X1]

0x401e38 LDR	Q19, [X19, X1]

0x401e3c STR	Q18, [X17, X1]

0x401e40 STR	Q19, [X2, X1]

0x401e44 ADD	X1, X1, #32

0x401e48 CMP	X30, X1

0x401e4c B.EQ	401ef8

  (15) 0x401e50 LDR	Q20, [X18, X1]

  (15) 0x401e54 ADD	X7, X1, #32

  (15) 0x401e58 ADD	X15, X1, #64

  (15) 0x401e5c ADD	X10, X1, #96

  (15) 0x401e60 ADD	X14, X1, #128

  (15) 0x401e64 LDR	Q21, [X19, X1]

  (15) 0x401e68 ADD	X13, X1, #160

  (15) 0x401e6c ADD	X12, X1, #192

  (15) 0x401e70 ADD	X11, X1, #224

  (15) 0x401e74 STR	Q20, [X17, X1]

  (15) 0x401e78 STR	Q21, [X2, X1]

  (15) 0x401e7c ADD	X1, X1, #256

  (15) 0x401e80 LDR	Q22, [X18, X7]

  (15) 0x401e84 LDR	Q23, [X19, X7]

  (15) 0x401e88 STR	Q22, [X17, X7]

  (15) 0x401e8c STR	Q23, [X2, X7]

  (15) 0x401e90 LDR	Q24, [X18, X15]

  (15) 0x401e94 LDR	Q25, [X19, X15]

  (15) 0x401e98 STR	Q24, [X17, X15]

  (15) 0x401e9c STR	Q25, [X2, X15]

  (15) 0x401ea0 LDR	Q26, [X18, X10]

  (15) 0x401ea4 LDR	Q27, [X19, X10]

  (15) 0x401ea8 STR	Q26, [X17, X10]

  (15) 0x401eac STR	Q27, [X2, X10]

  (15) 0x401eb0 LDR	Q28, [X18, X14]

  (15) 0x401eb4 LDR	Q29, [X19, X14]

  (15) 0x401eb8 STR	Q28, [X17, X14]

  (15) 0x401ebc STR	Q29, [X2, X14]

  (15) 0x401ec0 LDR	Q30, [X18, X13]

  (15) 0x401ec4 LDR	Q31, [X19, X13]

  (15) 0x401ec8 STR	Q30, [X17, X13]

  (15) 0x401ecc STR	Q31, [X2, X13]

  (15) 0x401ed0 LDR	Q0, [X18, X12]

  (15) 0x401ed4 LDR	Q1, [X19, X12]

  (15) 0x401ed8 STR	Q0, [X17, X12]

  (15) 0x401edc STR	Q1, [X2, X12]

  (15) 0x401ee0 LDR	Q2, [X18, X11]

  (15) 0x401ee4 LDR	Q3, [X19, X11]

  (15) 0x401ee8 STR	Q2, [X17, X11]

  (15) 0x401eec STR	Q3, [X2, X11]

  (15) 0x401ef0 CMP	X30, X1

  (15) 0x401ef4 B.NE	401e50

0x401ef8 AND	X14, X4, #8062

0x401efc ANDS	XZR, X4, #4160

0x401f00 B.EQ	401f2c

0x401f04 ADD	X0, X0, X14

0x401f08 SUB	X4, X4, X14

0x401f0c WHILELO	P7.D, XZR, X4

0x401f10 ADD	X8, X8, X0,LSL #3

0x401f14 LD1D	{Z4.D}, P7/Z, [X9, X0,LSL #3]

0x401f18 ST1D	{Z4.D}, P7, [X8, MUL VL]

0x401f1c CNTD	X17, ALL

0x401f20 ADD	X9, X9, X0,LSL #3

0x401f24 WHILELO	P0.D, X17, X4

0x401f28 B.NE	401f44

0x401f2c LDR	X19, [SP, #16]

0x401f30 LDP	X29, X30, [SP], #32

0x401f34 RET

0x401f38 ADD	X4, X4, #1

0x401f3c MOVZ	X2, #0

0x401f40 B	401d30

0x401f44 LDR	X19, [SP, #16]

0x401f48 LD1D	{Z5.D}, P0/Z, [X9, #1, MUL VL]

0x401f4c ST1D	{Z5.D}, P0, [X8, #1, MUL VL]

0x401f50 LDP	X29, X30, [SP], #32

0x401f54 RET

0x401f58 SUB	X18, X5, X0

0x401f5c ANDS	X30, X18, #4224

0x401f60 B.EQ	401ff0

0x401f64 CMP	X30, #1

0x401f68 B.EQ	401fdc

0x401f6c CMP	X30, #2

0x401f70 B.EQ	401fd0

0x401f74 CMP	X30, #3

0x401f78 B.EQ	401fc4

0x401f7c CMP	X30, #4

0x401f80 B.EQ	401fb8

0x401f84 CMP	X30, #5

0x401f88 B.EQ	401fac

0x401f8c CMP	X30, #6

0x401f90 B.EQ	401fa0

0x401f94 LDR	D6, [X9, X0,LSL #3]

0x401f98 STR	D6, [X8, X0,LSL #3]

0x401f9c ADD	X0, X0, #1

0x401fa0 LDR	D7, [X9, X0,LSL #3]

0x401fa4 STR	D7, [X8, X0,LSL #3]

0x401fa8 ADD	X0, X0, #1

0x401fac LDR	D16, [X9, X0,LSL #3]

0x401fb0 STR	D16, [X8, X0,LSL #3]

0x401fb4 ADD	X0, X0, #1

0x401fb8 LDR	D17, [X9, X0,LSL #3]

0x401fbc STR	D17, [X8, X0,LSL #3]

0x401fc0 ADD	X0, X0, #1

0x401fc4 LDR	D18, [X9, X0,LSL #3]

0x401fc8 STR	D18, [X8, X0,LSL #3]

0x401fcc ADD	X0, X0, #1

0x401fd0 LDR	D19, [X9, X0,LSL #3]

0x401fd4 STR	D19, [X8, X0,LSL #3]

0x401fd8 ADD	X0, X0, #1

0x401fdc LDR	D20, [X9, X0,LSL #3]

0x401fe0 STR	D20, [X8, X0,LSL #3]

0x401fe4 ADD	X0, X0, #1

0x401fe8 CMP	X5, X0

0x401fec B.EQ	401f2c

  (14) 0x401ff0 LDR	D21, [X9, X0,LSL #3]

  (14) 0x401ff4 ADD	X19, X0, #1

  (14) 0x401ff8 ADD	X1, X0, #2

  (14) 0x401ffc ADD	X16, X0, #3

  (14) 0x402000 ADD	X6, X0, #4

  (14) 0x402004 ADD	X7, X0, #5

  (14) 0x402008 ADD	X3, X0, #6

  (14) 0x40200c ADD	X2, X0, #7

  (14) 0x402010 STR	D21, [X8, X0,LSL #3]

  (14) 0x402014 ADD	X0, X0, #8

  (14) 0x402018 LDR	D22, [X9, X19,LSL #3]

  (14) 0x40201c STR	D22, [X8, X19,LSL #3]

  (14) 0x402020 LDR	D23, [X9, X1,LSL #3]

  (14) 0x402024 STR	D23, [X8, X1,LSL #3]

  (14) 0x402028 LDR	D24, [X9, X16,LSL #3]

  (14) 0x40202c STR	D24, [X8, X16,LSL #3]

  (14) 0x402030 LDR	D25, [X9, X6,LSL #3]

  (14) 0x402034 STR	D25, [X8, X6,LSL #3]

  (14) 0x402038 LDR	D26, [X9, X7,LSL #3]

  (14) 0x40203c STR	D26, [X8, X7,LSL #3]

  (14) 0x402040 LDR	D27, [X9, X3,LSL #3]

  (14) 0x402044 STR	D27, [X8, X3,LSL #3]

  (14) 0x402048 LDR	D28, [X9, X2,LSL #3]

  (14) 0x40204c STR	D28, [X8, X2,LSL #3]

  (14) 0x402050 CMP	X5, X0

  (14) 0x402054 B.NE	401ff0

0x402058 B	401f2c

0x40205c LDR	Q30, [X18]

0x402060 MOVZ	X1, #32

0x402064 LDR	Q31, [X19]

0x402068 STR	Q30, [X17]

0x40206c STR	Q31, [X2]

0x402070 B	401dd0

0x402074 MOVZ	X14, #0

0x402078 B	401f04

/home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c: 322 - 324

--------------------------------------------------------------------------------

322: #pragma omp parallel for

323: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

324: 	    c[j] = a[j];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.15
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	micro-operation queue,
Function	main._omp_fn.4
Source	stream.c:322-324
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.88
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	17.88
CQA cycles if fully vectorized	13.50
Front-end cycles	17.88
P0 cycles	13.50
P1 cycles	13.50
P2 cycles	16.00
P3 cycles	16.00
P4 cycles	16.00
P5 cycles	16.00
P6 cycles	10.50
P7 cycles	10.50
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	17.50
P11 cycles	17.17
P12 cycles	17.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	143.00
Nb uops	143.00
Nb loads	NA
Nb stores	23.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.52
Bytes prefetched	0.00
Bytes loaded	416.00
Bytes stored	344.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.51
Vectorization ratio load	64.00
Vectorization ratio store	69.57
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	38.29
Vector-efficiency ratio load	47.00
Vector-efficiency ratio store	46.74
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.15
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	micro-operation queue,
Function	main._omp_fn.4
Source	stream.c:322-324
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.88
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	17.88
CQA cycles if fully vectorized	13.50
Front-end cycles	17.88
P0 cycles	13.50
P1 cycles	13.50
P2 cycles	16.00
P3 cycles	16.00
P4 cycles	16.00
P5 cycles	16.00
P6 cycles	10.50
P7 cycles	10.50
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	17.50
P11 cycles	17.17
P12 cycles	17.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	143.00
Nb uops	143.00
Nb loads	NA
Nb stores	23.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.52
Bytes prefetched	0.00
Bytes loaded	416.00
Bytes stored	344.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	40.51
Vectorization ratio load	64.00
Vectorization ratio store	69.57
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	38.29
Vector-efficiency ratio load	47.00
Vector-efficiency ratio store	46.74
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.4
Source file and lines	stream.c:322-324
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:322-324.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.88 to 15.50 cycles (1.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 38% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 17.88 to 13.50 cycles (1.32x speedup).

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

64% of VPU loads are used in vector version.
69% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 416 bytes. The binary loop is storing 344 bytes.

General properties

nb instructions	143
nb uops	143
loop length	572
used w registers	0
used x registers	23
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	14
used v registers	0
used z registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.88 cycles
front end	17.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.50	13.50	16.00	16.00	16.00	16.00	10.50	10.50	1.00	1.00	17.50	17.17	17.33	0.00	0.00
cycles	13.50	13.50	16.00	16.00	16.00	16.00	10.50	10.50	1.00	1.00	17.50	17.17	17.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.88
Dispatch	17.50
Overall L1	17.88

Vectorization ratios

all	40%
load	64%
store	69%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	38%
load	47%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.88 cycles. At this rate:

24% of peak load performance is reached (23.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
40% of peak store performance is reached (19.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 401f38

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X0, X4, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 401f2c <main._omp_fn.4+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, 402d40 <checkSTREAMresults+0x5c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X6, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X7, [X3, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X10, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X8, X9, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
ADD X17, X8, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X12, X17, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 401f58 <main._omp_fn.4+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 402074 <main._omp_fn.4+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X15, X4, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X30, X15, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X30, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X5, X16, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X6, X3, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401e50 <main._omp_fn.4+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401e34 <main._omp_fn.4+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401e20 <main._omp_fn.4+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401e0c <main._omp_fn.4+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401df8 <main._omp_fn.4+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401de4 <main._omp_fn.4+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 40205c <main._omp_fn.4+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q0, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q1, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q0, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q1, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q2, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q3, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q2, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q3, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q4, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q5, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q4, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q5, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q6, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q7, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q6, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q7, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q16, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q17, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q16, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q17, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q18, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q19, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q18, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q19, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401ef8 <main._omp_fn.4+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X14, X4, #8062	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS XZR, X4, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401f2c <main._omp_fn.4+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X4, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P7.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
ADD X8, X8, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z4.D}, P7/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z4.D}, P7, [X8, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X9, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, X17, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.NE 401f44 <main._omp_fn.4+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 401d30 <main._omp_fn.4+0x30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LD1D {Z5.D}, P0/Z, [X9, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z5.D}, P0, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X18, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X30, X18, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401ff0 <main._omp_fn.4+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fdc <main._omp_fn.4+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fd0 <main._omp_fn.4+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fc4 <main._omp_fn.4+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fb8 <main._omp_fn.4+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fac <main._omp_fn.4+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fa0 <main._omp_fn.4+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D6, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D7, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D16, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D17, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D18, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D19, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D20, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401f2c <main._omp_fn.4+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 401f2c <main._omp_fn.4+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
MOVZ X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q31, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q30, [X17]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q31, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
B 401dd0 <main._omp_fn.4+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 401f04 <main._omp_fn.4+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.4
Source file and lines	stream.c:322-324
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:322-324.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

40% of VPU instructions are used in vector version (process two or more data elements in vector registers):

64% of VPU loads are used in vector version.
69% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 416 bytes. The binary loop is storing 344 bytes.

General properties

nb instructions	143
nb uops	143
loop length	572
used w registers	0
used x registers	23
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	14
used v registers	0
used z registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.88 cycles
front end	17.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.50	13.50	16.00	16.00	16.00	16.00	10.50	10.50	1.00	1.00	17.50	17.17	17.33	0.00	0.00
cycles	13.50	13.50	16.00	16.00	16.00	16.00	10.50	10.50	1.00	1.00	17.50	17.17	17.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.88
Dispatch	17.50
Overall L1	17.88

Vectorization ratios

all	40%
load	64%
store	69%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	38%
load	47%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.88 cycles. At this rate:

24% of peak load performance is reached (23.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
40% of peak store performance is reached (19.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 401f38

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X0, X4, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 401f2c <main._omp_fn.4+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, 402d40 <checkSTREAMresults+0x5c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X6, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X7, [X3, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X10, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X8, X9, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
ADD X17, X8, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X12, X17, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 401f58 <main._omp_fn.4+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 402074 <main._omp_fn.4+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X15, X4, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X30, X15, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X30, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X5, X16, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X6, X3, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401e50 <main._omp_fn.4+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401e34 <main._omp_fn.4+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401e20 <main._omp_fn.4+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401e0c <main._omp_fn.4+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401df8 <main._omp_fn.4+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401de4 <main._omp_fn.4+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 40205c <main._omp_fn.4+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q0, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q1, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q0, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q1, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q2, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q3, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q2, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q3, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q4, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q5, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q4, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q5, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q6, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q7, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q6, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q7, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q16, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q17, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q16, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q17, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q18, [X18, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q19, [X19, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q18, [X17, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q19, [X2, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X1, X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401ef8 <main._omp_fn.4+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X14, X4, #8062	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS XZR, X4, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401f2c <main._omp_fn.4+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X4, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P7.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
ADD X8, X8, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z4.D}, P7/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z4.D}, P7, [X8, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X9, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, X17, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.NE 401f44 <main._omp_fn.4+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 401d30 <main._omp_fn.4+0x30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LD1D {Z5.D}, P0/Z, [X9, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z5.D}, P0, [X8, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X18, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X30, X18, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401ff0 <main._omp_fn.4+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fdc <main._omp_fn.4+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fd0 <main._omp_fn.4+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fc4 <main._omp_fn.4+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fb8 <main._omp_fn.4+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fac <main._omp_fn.4+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401fa0 <main._omp_fn.4+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D6, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D7, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D16, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D17, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D18, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D18, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D19, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D20, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
STR D20, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401f2c <main._omp_fn.4+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 401f2c <main._omp_fn.4+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
MOVZ X1, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q31, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q30, [X17]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q31, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
B 401dd0 <main._omp_fn.4+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 401f04 <main._omp_fn.4+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code