OV - exec - Loop 10

	Loop Id: 10	Module: exec	Source: stream.c:334-336	Coverage: 0.00%

0x4018dc MADD	X1, X4, X1, X0

0x4018e0 ADD	X5, X4, X1

0x4018e4 CMP	X1, X5

0x4018e8 B.GE	401b58

0x4018ec ADRP	X3, 4018ec

0x4018f0 UBFM	X6, X1, #61, #60

0x4018f4 LDR	D31, [X20]

0x4018f8 ADD	X7, X6, #8

0x4018fc LDR	X8, [X3, #3312]

0x401900 LDP	X17, X9, [X8]

0x401904 ADD	X18, X17, X1,LSL #3

0x401908 ADD	X10, X9, X7

0x40190c SUB	X11, X18, X10

0x401910 CMP	X11, #16

0x401914 B.LS	401b88

0x401918 SUB	X12, X4, #1

0x40191c CMP	X12, #2

0x401920 B.LS	401ce8

0x401924 UBFM	X14, X4, #2, #63

0x401928 ADD	X30, X9, X6

0x40192c DUP	V30.2D, V31.D[0]

0x401930 UBFM	X20, X14, #59, #58

0x401934 ADD	X19, X30, #16

0x401938 SUB	X15, X20, #32

0x40193c MOVZ	X0, #0

0x401940 UBFM	X16, X15, #5, #63

0x401944 ADD	X2, X18, #16

0x401948 ADD	X5, X16, #1

0x40194c ANDS	X3, X5, #4224

0x401950 B.EQ	401a34

0x401954 CMP	X3, #1

0x401958 B.EQ	401a10

0x40195c CMP	X3, #2

0x401960 B.EQ	4019f4

0x401964 CMP	X3, #3

0x401968 B.EQ	4019d8

0x40196c CMP	X3, #4

0x401970 B.EQ	4019bc

0x401974 CMP	X3, #5

0x401978 B.EQ	4019a0

0x40197c CMP	X3, #6

0x401980 B.NE	401cc8

0x401984 LDR	Q28, [X30, X0]

0x401988 LDR	Q4, [X19, X0]

0x40198c FMUL	V5.2D, V28.2D, V30.2D

0x401990 FMUL	V6.2D, V4.2D, V30.2D

0x401994 STR	Q5, [X18, X0]

0x401998 STR	Q6, [X2, X0]

0x40199c ADD	X0, X0, #32

0x4019a0 LDR	Q26, [X30, X0]

0x4019a4 LDR	Q27, [X19, X0]

0x4019a8 FMUL	V7.2D, V26.2D, V30.2D

0x4019ac FMUL	V16.2D, V27.2D, V30.2D

0x4019b0 STR	Q7, [X18, X0]

0x4019b4 STR	Q16, [X2, X0]

0x4019b8 ADD	X0, X0, #32

0x4019bc LDR	Q24, [X30, X0]

0x4019c0 LDR	Q25, [X19, X0]

0x4019c4 FMUL	V17.2D, V24.2D, V30.2D

0x4019c8 FMUL	V18.2D, V25.2D, V30.2D

0x4019cc STR	Q17, [X18, X0]

0x4019d0 STR	Q18, [X2, X0]

0x4019d4 ADD	X0, X0, #32

0x4019d8 LDR	Q23, [X30, X0]

0x4019dc LDR	Q29, [X19, X0]

0x4019e0 FMUL	V19.2D, V23.2D, V30.2D

0x4019e4 FMUL	V20.2D, V29.2D, V30.2D

0x4019e8 STR	Q19, [X18, X0]

0x4019ec STR	Q20, [X2, X0]

0x4019f0 ADD	X0, X0, #32

0x4019f4 LDR	Q21, [X30, X0]

0x4019f8 LDR	Q22, [X19, X0]

0x4019fc FMUL	V1.2D, V21.2D, V30.2D

0x401a00 FMUL	V0.2D, V22.2D, V30.2D

0x401a04 STR	Q1, [X18, X0]

0x401a08 STR	Q0, [X2, X0]

0x401a0c ADD	X0, X0, #32

0x401a10 LDR	Q2, [X30, X0]

0x401a14 LDR	Q3, [X19, X0]

0x401a18 FMUL	V28.2D, V2.2D, V30.2D

0x401a1c FMUL	V4.2D, V3.2D, V30.2D

0x401a20 STR	Q28, [X18, X0]

0x401a24 STR	Q4, [X2, X0]

0x401a28 ADD	X0, X0, #32

0x401a2c CMP	X20, X0

0x401a30 B.EQ	401b1c

  (12) 0x401a34 LDR	Q5, [X30, X0]

  (12) 0x401a38 ADD	X6, X0, #32

  (12) 0x401a3c ADD	X8, X0, #64

  (12) 0x401a40 ADD	X7, X0, #96

  (12) 0x401a44 ADD	X10, X0, #128

  (12) 0x401a48 LDR	Q6, [X19, X0]

  (12) 0x401a4c ADD	X13, X0, #160

  (12) 0x401a50 ADD	X12, X0, #192

  (12) 0x401a54 ADD	X11, X0, #224

  (12) 0x401a58 FMUL	V26.2D, V5.2D, V30.2D

  (12) 0x401a5c FMUL	V27.2D, V6.2D, V30.2D

  (12) 0x401a60 STR	Q26, [X18, X0]

  (12) 0x401a64 STR	Q27, [X2, X0]

  (12) 0x401a68 ADD	X0, X0, #256

  (12) 0x401a6c LDR	Q7, [X30, X6]

  (12) 0x401a70 LDR	Q16, [X19, X6]

  (12) 0x401a74 FMUL	V24.2D, V7.2D, V30.2D

  (12) 0x401a78 FMUL	V25.2D, V16.2D, V30.2D

  (12) 0x401a7c STR	Q24, [X18, X6]

  (12) 0x401a80 STR	Q25, [X2, X6]

  (12) 0x401a84 LDR	Q17, [X30, X8]

  (12) 0x401a88 LDR	Q18, [X19, X8]

  (12) 0x401a8c FMUL	V23.2D, V17.2D, V30.2D

  (12) 0x401a90 FMUL	V29.2D, V18.2D, V30.2D

  (12) 0x401a94 STR	Q23, [X18, X8]

  (12) 0x401a98 STR	Q29, [X2, X8]

  (12) 0x401a9c LDR	Q19, [X30, X7]

  (12) 0x401aa0 LDR	Q20, [X19, X7]

  (12) 0x401aa4 FMUL	V21.2D, V19.2D, V30.2D

  (12) 0x401aa8 FMUL	V22.2D, V20.2D, V30.2D

  (12) 0x401aac STR	Q21, [X18, X7]

  (12) 0x401ab0 STR	Q22, [X2, X7]

  (12) 0x401ab4 LDR	Q1, [X30, X10]

  (12) 0x401ab8 LDR	Q0, [X19, X10]

  (12) 0x401abc FMUL	V3.2D, V1.2D, V30.2D

  (12) 0x401ac0 FMUL	V2.2D, V0.2D, V30.2D

  (12) 0x401ac4 STR	Q3, [X18, X10]

  (12) 0x401ac8 STR	Q2, [X2, X10]

  (12) 0x401acc LDR	Q28, [X30, X13]

  (12) 0x401ad0 LDR	Q4, [X19, X13]

  (12) 0x401ad4 FMUL	V5.2D, V28.2D, V30.2D

  (12) 0x401ad8 FMUL	V6.2D, V4.2D, V30.2D

  (12) 0x401adc STR	Q5, [X18, X13]

  (12) 0x401ae0 STR	Q6, [X2, X13]

  (12) 0x401ae4 LDR	Q26, [X30, X12]

  (12) 0x401ae8 LDR	Q27, [X19, X12]

  (12) 0x401aec FMUL	V7.2D, V26.2D, V30.2D

  (12) 0x401af0 FMUL	V16.2D, V27.2D, V30.2D

  (12) 0x401af4 STR	Q7, [X18, X12]

  (12) 0x401af8 STR	Q16, [X2, X12]

  (12) 0x401afc LDR	Q24, [X30, X11]

  (12) 0x401b00 LDR	Q25, [X19, X11]

  (12) 0x401b04 FMUL	V17.2D, V24.2D, V30.2D

  (12) 0x401b08 FMUL	V18.2D, V25.2D, V30.2D

  (12) 0x401b0c STR	Q17, [X18, X11]

  (12) 0x401b10 STR	Q18, [X2, X11]

  (12) 0x401b14 CMP	X20, X0

  (12) 0x401b18 B.NE	401a34

0x401b1c AND	X13, X4, #8062

0x401b20 ANDS	XZR, X4, #4160

0x401b24 B.EQ	401b58

0x401b28 ADD	X1, X1, X13

0x401b2c SUB	X4, X4, X13

0x401b30 DUP	Z31.D, Z31.D[0]

0x401b34 WHILELO	P7.D, XZR, X4

0x401b38 ADD	X17, X17, X1,LSL #3

0x401b3c LD1D	{Z30.D}, P7/Z, [X9, X1,LSL #3]

0x401b40 FMUL	Z23.D, Z30.D, Z31.D

0x401b44 ST1D	{Z23.D}, P7, [X17, MUL VL]

0x401b48 CNTD	X18, ALL

0x401b4c ADD	X9, X9, X1,LSL #3

0x401b50 WHILELO	P0.D, X18, X4

0x401b54 B.NE	401b70

0x401b58 LDP	X19, X20, [SP, #16]

0x401b5c LDP	X29, X30, [SP], #32

0x401b60 RET

0x401b64 ADD	X4, X4, #1

0x401b68 MOVZ	X0, #0

0x401b6c B	4018dc

0x401b70 LD1D	{Z29.D}, P0/Z, [X9, #1, MUL VL]

0x401b74 FMUL	Z19.D, Z29.D, Z31.D

0x401b78 ST1D	{Z19.D}, P0, [X17, #1, MUL VL]

0x401b7c LDP	X19, X20, [SP, #16]

0x401b80 LDP	X29, X30, [SP], #32

0x401b84 RET

0x401b88 SUB	X14, X5, X1

0x401b8c ANDS	X30, X14, #4224

0x401b90 B.EQ	401c3c

0x401b94 CMP	X30, #1

0x401b98 B.EQ	401c24

0x401b9c CMP	X30, #2

0x401ba0 B.EQ	401c14

0x401ba4 CMP	X30, #3

0x401ba8 B.EQ	401c04

0x401bac CMP	X30, #4

0x401bb0 B.EQ	401bf4

0x401bb4 CMP	X30, #5

0x401bb8 B.EQ	401be4

0x401bbc CMP	X30, #6

0x401bc0 B.EQ	401bd4

0x401bc4 LDR	D20, [X9, X1,LSL #3]

0x401bc8 FMUL	D21, D20, D31

0x401bcc STR	D21, [X17, X1,LSL #3]

0x401bd0 ADD	X1, X1, #1

0x401bd4 LDR	D22, [X9, X1,LSL #3]

0x401bd8 FMUL	D1, D22, D31

0x401bdc STR	D1, [X17, X1,LSL #3]

0x401be0 ADD	X1, X1, #1

0x401be4 LDR	D0, [X9, X1,LSL #3]

0x401be8 FMUL	D3, D0, D31

0x401bec STR	D3, [X17, X1,LSL #3]

0x401bf0 ADD	X1, X1, #1

0x401bf4 LDR	D2, [X9, X1,LSL #3]

0x401bf8 FMUL	D28, D2, D31

0x401bfc STR	D28, [X17, X1,LSL #3]

0x401c00 ADD	X1, X1, #1

0x401c04 LDR	D4, [X9, X1,LSL #3]

0x401c08 FMUL	D5, D4, D31

0x401c0c STR	D5, [X17, X1,LSL #3]

0x401c10 ADD	X1, X1, #1

0x401c14 LDR	D6, [X9, X1,LSL #3]

0x401c18 FMUL	D26, D6, D31

0x401c1c STR	D26, [X17, X1,LSL #3]

0x401c20 ADD	X1, X1, #1

0x401c24 LDR	D27, [X9, X1,LSL #3]

0x401c28 FMUL	D7, D27, D31

0x401c2c STR	D7, [X17, X1,LSL #3]

0x401c30 ADD	X1, X1, #1

0x401c34 CMP	X5, X1

0x401c38 B.EQ	401b58

  (11) 0x401c3c LDR	D16, [X9, X1,LSL #3]

  (11) 0x401c40 ADD	X20, X1, #1

  (11) 0x401c44 ADD	X15, X1, #2

  (11) 0x401c48 ADD	X19, X1, #3

  (11) 0x401c4c ADD	X16, X1, #4

  (11) 0x401c50 ADD	X0, X1, #5

  (11) 0x401c54 ADD	X3, X1, #6

  (11) 0x401c58 ADD	X2, X1, #7

  (11) 0x401c5c FMUL	D24, D16, D31

  (11) 0x401c60 STR	D24, [X17, X1,LSL #3]

  (11) 0x401c64 ADD	X1, X1, #8

  (11) 0x401c68 LDR	D25, [X9, X20,LSL #3]

  (11) 0x401c6c FMUL	D17, D25, D31

  (11) 0x401c70 STR	D17, [X17, X20,LSL #3]

  (11) 0x401c74 LDR	D18, [X9, X15,LSL #3]

  (11) 0x401c78 FMUL	D30, D18, D31

  (11) 0x401c7c STR	D30, [X17, X15,LSL #3]

  (11) 0x401c80 LDR	D23, [X9, X19,LSL #3]

  (11) 0x401c84 FMUL	D29, D23, D31

  (11) 0x401c88 STR	D29, [X17, X19,LSL #3]

  (11) 0x401c8c LDR	D19, [X9, X16,LSL #3]

  (11) 0x401c90 FMUL	D20, D19, D31

  (11) 0x401c94 STR	D20, [X17, X16,LSL #3]

  (11) 0x401c98 LDR	D21, [X9, X0,LSL #3]

  (11) 0x401c9c FMUL	D22, D21, D31

  (11) 0x401ca0 STR	D22, [X17, X0,LSL #3]

  (11) 0x401ca4 LDR	D1, [X9, X3,LSL #3]

  (11) 0x401ca8 FMUL	D0, D1, D31

  (11) 0x401cac STR	D0, [X17, X3,LSL #3]

  (11) 0x401cb0 LDR	D3, [X9, X2,LSL #3]

  (11) 0x401cb4 FMUL	D2, D3, D31

  (11) 0x401cb8 STR	D2, [X17, X2,LSL #3]

  (11) 0x401cbc CMP	X5, X1

  (11) 0x401cc0 B.NE	401c3c

0x401cc4 B	401b58

0x401cc8 LDR	Q1, [X30]

0x401ccc MOVZ	X0, #32

0x401cd0 LDR	Q2, [X19]

0x401cd4 FMUL	V0.2D, V1.2D, V30.2D

0x401cd8 FMUL	V3.2D, V2.2D, V30.2D

0x401cdc STR	Q0, [X18]

0x401ce0 STR	Q3, [X2]

0x401ce4 B	401984

0x401ce8 MOVZ	X13, #0

0x401cec B	401b28

/home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c: 334 - 336

--------------------------------------------------------------------------------

334: #pragma omp parallel for

335: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

336: 	    b[j] = scalar*c[j];

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.08
CQA speedup if fully vectorized	1.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	main._omp_fn.5
Source	stream.c:334-336
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.13
CQA cycles if no scalar integer	15.83
CQA cycles if FP arith vectorized	19.59
CQA cycles if fully vectorized	13.66
Front-end cycles	21.13
P0 cycles	13.50
P1 cycles	13.50
P2 cycles	16.00
P3 cycles	16.00
P4 cycles	16.00
P5 cycles	16.00
P6 cycles	12.00
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	17.83
P11 cycles	17.50
P12 cycles	17.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	169.00
Nb uops	169.00
Nb loads	NA
Nb stores	23.00
Nb stack references	4.00
FLOP/cycle	2.04
Nb FLOP add-sub	0.00
Nb FLOP mul	43.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	37.11
Bytes prefetched	0.00
Bytes loaded	440.00
Bytes stored	344.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	49.02
Vectorization ratio load	66.67
Vectorization ratio store	69.57
Vectorization ratio mul	69.57
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	8.33
Vector-efficiency ratio all	40.69
Vector-efficiency ratio load	45.83
Vector-efficiency ratio store	46.74
Vector-efficiency ratio mul	46.74
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	29.17

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.08
CQA speedup if fully vectorized	1.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	main._omp_fn.5
Source	stream.c:334-336
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.13
CQA cycles if no scalar integer	15.83
CQA cycles if FP arith vectorized	19.59
CQA cycles if fully vectorized	13.66
Front-end cycles	21.13
P0 cycles	13.50
P1 cycles	13.50
P2 cycles	16.00
P3 cycles	16.00
P4 cycles	16.00
P5 cycles	16.00
P6 cycles	12.00
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	17.83
P11 cycles	17.50
P12 cycles	17.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	169.00
Nb uops	169.00
Nb loads	NA
Nb stores	23.00
Nb stack references	4.00
FLOP/cycle	2.04
Nb FLOP add-sub	0.00
Nb FLOP mul	43.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	37.11
Bytes prefetched	0.00
Bytes loaded	440.00
Bytes stored	344.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	49.02
Vectorization ratio load	66.67
Vectorization ratio store	69.57
Vectorization ratio mul	69.57
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	8.33
Vector-efficiency ratio all	40.69
Vector-efficiency ratio load	45.83
Vector-efficiency ratio store	46.74
Vector-efficiency ratio mul	46.74
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	29.17

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main._omp_fn.5
Source file and lines	stream.c:334-336
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:334-336.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.13 to 15.83 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 40% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 21.13 to 13.66 cycles (1.55x speedup).

Details

49% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
69% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
69% of VPU multiply instructions are used in vector version.
8% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 43 FP arithmetical operations:

43: multiply

The binary loop is loading 440 bytes. The binary loop is storing 344 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	169
nb uops	169
loop length	676
used w registers	0
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	15
used q registers	22
used v registers	24
used z registers	5
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.13 cycles
front end	21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.50	13.50	16.00	16.00	16.00	16.00	12.00	12.00	12.00	12.00	17.83	17.50	17.67	0.00	0.00
cycles	13.50	13.50	16.00	16.00	16.00	16.00	12.00	12.00	12.00	12.00	17.83	17.50	17.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.13
Dispatch	17.83
Overall L1	21.13

Vectorization ratios

INT

all	43%
load	66%
store	69%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	69%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	69%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	49%
load	66%
store	69%
mul	69%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	38%
load	45%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	29%

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	46%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	40%
load	45%
store	46%
mul	46%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.13 cycles. At this rate:

21% of peak load performance is reached (20.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.13 to 17.83 cycles (1.18x speedup).

ASM code

In the binary file, the address of the loop is: 401b64

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X1, X4, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 401b58 <main._omp_fn.5+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, 4018ec <main._omp_fn.5+0x44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X6, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X7, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X3, #3312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X17, X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
ADD X18, X17, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X11, X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 401b88 <main._omp_fn.5+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X12, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 401ce8 <main._omp_fn.5+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X14, X4, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X30, X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP V30.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
UBFM X20, X14, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X30, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X15, X20, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X15, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X3, X5, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401a34 <main._omp_fn.5+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401a10 <main._omp_fn.5+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4019f4 <main._omp_fn.5+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4019d8 <main._omp_fn.5+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4019bc <main._omp_fn.5+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4019a0 <main._omp_fn.5+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 401cc8 <main._omp_fn.5+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q28, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q4, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V5.2D, V28.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V4.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q5, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q6, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q26, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q27, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V7.2D, V26.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V16.2D, V27.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q7, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q16, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q24, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q25, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V17.2D, V24.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V18.2D, V25.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q17, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q18, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q23, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q29, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V19.2D, V23.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V20.2D, V29.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q19, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q20, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q21, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q22, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V1.2D, V21.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V0.2D, V22.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q1, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q0, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q2, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q3, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V28.2D, V2.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V4.2D, V3.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q28, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q4, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401b1c <main._omp_fn.5+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X13, X4, #8062	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS XZR, X4, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401b58 <main._omp_fn.5+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z31.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P7.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
ADD X17, X17, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z30.D}, P7/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z23.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z23.D}, P7, [X17, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X9, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, X18, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.NE 401b70 <main._omp_fn.5+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 4018dc <main._omp_fn.5+0x34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z29.D}, P0/Z, [X9, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z19.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z19.D}, P0, [X17, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X14, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X30, X14, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401c3c <main._omp_fn.5+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401c24 <main._omp_fn.5+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401c14 <main._omp_fn.5+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401c04 <main._omp_fn.5+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401bf4 <main._omp_fn.5+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401be4 <main._omp_fn.5+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401bd4 <main._omp_fn.5+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D21, D20, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D21, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D1, D22, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D1, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D3, D0, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D28, D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D28, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D5, D4, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D5, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D26, D6, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D26, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D7, D27, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D7, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401b58 <main._omp_fn.5+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 401b58 <main._omp_fn.5+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
MOVZ X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V0.2D, V1.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V3.2D, V2.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q0, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q3, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
B 401984 <main._omp_fn.5+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 401b28 <main._omp_fn.5+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main._omp_fn.5
Source file and lines	stream.c:334-336
Module	exec

The loop is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:334-336.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

49% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
69% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
69% of VPU multiply instructions are used in vector version.
8% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 43 FP arithmetical operations:

43: multiply

The binary loop is loading 440 bytes. The binary loop is storing 344 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	169
nb uops	169
loop length	676
used w registers	0
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	15
used q registers	22
used v registers	24
used z registers	5
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.13 cycles
front end	21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.50	13.50	16.00	16.00	16.00	16.00	12.00	12.00	12.00	12.00	17.83	17.50	17.67	0.00	0.00
cycles	13.50	13.50	16.00	16.00	16.00	16.00	12.00	12.00	12.00	12.00	17.83	17.50	17.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.13
Dispatch	17.83
Overall L1	21.13

Vectorization ratios

INT

all	43%
load	66%
store	69%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	69%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	69%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	49%
load	66%
store	69%
mul	69%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	38%
load	45%
store	46%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	29%

all	46%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	46%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	40%
load	45%
store	46%
mul	46%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.13 cycles. At this rate:

21% of peak load performance is reached (20.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 401b64

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MADD X1, X4, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 401b58 <main._omp_fn.5+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, 4018ec <main._omp_fn.5+0x44>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X6, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X7, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X3, #3312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X17, X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
ADD X18, X17, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X11, X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 401b88 <main._omp_fn.5+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X12, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 401ce8 <main._omp_fn.5+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X14, X4, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X30, X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP V30.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
UBFM X20, X14, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X30, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X15, X20, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X15, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X3, X5, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401a34 <main._omp_fn.5+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401a10 <main._omp_fn.5+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4019f4 <main._omp_fn.5+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4019d8 <main._omp_fn.5+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4019bc <main._omp_fn.5+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4019a0 <main._omp_fn.5+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 401cc8 <main._omp_fn.5+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q28, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q4, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V5.2D, V28.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V4.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q5, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q6, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q26, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q27, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V7.2D, V26.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V16.2D, V27.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q7, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q16, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q24, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q25, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V17.2D, V24.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V18.2D, V25.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q17, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q18, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q23, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q29, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V19.2D, V23.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V20.2D, V29.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q19, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q20, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q21, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q22, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V1.2D, V21.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V0.2D, V22.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q1, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q0, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q2, [X30, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q3, [X19, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V28.2D, V2.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V4.2D, V3.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q28, [X18, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q4, [X2, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401b1c <main._omp_fn.5+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X13, X4, #8062	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS XZR, X4, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401b58 <main._omp_fn.5+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z31.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P7.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
ADD X17, X17, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z30.D}, P7/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z23.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z23.D}, P7, [X17, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X9, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, X18, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.NE 401b70 <main._omp_fn.5+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 4018dc <main._omp_fn.5+0x34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z29.D}, P0/Z, [X9, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z19.D, Z29.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z19.D}, P0, [X17, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50	vect (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
LDP X29, X30, [SP], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X14, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X30, X14, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401c3c <main._omp_fn.5+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401c24 <main._omp_fn.5+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401c14 <main._omp_fn.5+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401c04 <main._omp_fn.5+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401bf4 <main._omp_fn.5+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401be4 <main._omp_fn.5+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X30, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401bd4 <main._omp_fn.5+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D21, D20, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D21, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D1, D22, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D1, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D3, D0, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D3, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D28, D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D28, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D4, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D5, D4, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D5, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D6, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D26, D6, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D26, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL D7, D27, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
STR D7, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 401b58 <main._omp_fn.5+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 401b58 <main._omp_fn.5+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
MOVZ X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
FMUL V0.2D, V1.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V3.2D, V2.2D, V30.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
STR Q0, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q3, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (50.0%)
B 401984 <main._omp_fn.5+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 401b28 <main._omp_fn.5+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code