OV - exec - Function checkSTREAMresults

	Function: checkSTREAMresults	Module: exec	Source: stream.c:456-571 [...]	Coverage (incl. loops): 0.07% \| (excl. loops): 0.00%

/home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c: 456 - 571

--------------------------------------------------------------------------------

456: {

[...]

472: 	for (k=0; k<NTIMES; k++)

473:         {

474:             cj = aj;

475:             bj = scalar*cj;

476:             cj = aj+bj;

477:             aj = bj+scalar*cj;

[...]

484: 	for (j=0; j<STREAM_ARRAY_SIZE; j++) {

485: 		aSumErr += abs(a[j] - aj);

486: 		bSumErr += abs(b[j] - bj);

487: 		cSumErr += abs(c[j] - cj);

488: 		// if (j == 417) printf("Index 417: c[j]: %f, cj: %f\n",c[j],cj);	// MCCALPIN

489: 	}

490: 	aAvgErr = aSumErr / (STREAM_TYPE) STREAM_ARRAY_SIZE;

491: 	bAvgErr = bSumErr / (STREAM_TYPE) STREAM_ARRAY_SIZE;

[...]

506: 	if (abs(aAvgErr/aj) > epsilon) {

507: 		err++;

508: 		printf ("Failed Validation on array a[], AvgRelAbsErr > epsilon (%e)\n",epsilon);

509: 		printf ("     Expected Value: %e, AvgAbsErr: %e, AvgRelAbsErr: %e\n",aj,aAvgErr,abs(aAvgErr)/aj);

510: 		ierr = 0;

511: 		for (j=0; j<STREAM_ARRAY_SIZE; j++) {

512: 			if (abs(a[j]/aj-1.0) > epsilon) {

[...]

522: 		printf("     For array a[], %d errors were found.\n",ierr);

523: 	}

524: 	if (abs(bAvgErr/bj) > epsilon) {

525: 		err++;

526: 		printf ("Failed Validation on array b[], AvgRelAbsErr > epsilon (%e)\n",epsilon);

527: 		printf ("     Expected Value: %e, AvgAbsErr: %e, AvgRelAbsErr: %e\n",bj,bAvgErr,abs(bAvgErr)/bj);

528: 		printf ("     AvgRelAbsErr > Epsilon (%e)\n",epsilon);

529: 		ierr = 0;

530: 		for (j=0; j<STREAM_ARRAY_SIZE; j++) {

531: 			if (abs(b[j]/bj-1.0) > epsilon) {

[...]

541: 		printf("     For array b[], %d errors were found.\n",ierr);

542: 	}

543: 	if (abs(cAvgErr/cj) > epsilon) {

544: 		err++;

545: 		printf ("Failed Validation on array c[], AvgRelAbsErr > epsilon (%e)\n",epsilon);

546: 		printf ("     Expected Value: %e, AvgAbsErr: %e, AvgRelAbsErr: %e\n",cj,cAvgErr,abs(cAvgErr)/cj);

547: 		printf ("     AvgRelAbsErr > Epsilon (%e)\n",epsilon);

548: 		ierr = 0;

549: 		for (j=0; j<STREAM_ARRAY_SIZE; j++) {

550: 			if (abs(c[j]/cj-1.0) > epsilon) {

[...]

560: 		printf("     For array c[], %d errors were found.\n",ierr);

561: 	}

562: 	if (err == 0) {

563: 		printf ("Solution Validates: avg error less than %e on all three arrays\n",epsilon);

[...]

571: }

0x401c70 STP	D11, D10, [SP, #928]!

0x401c74 STP	D9, D8, [SP, #16]

0x401c78 STP	X29, X30, [SP, #32]

0x401c7c STR	X28, [SP, #48]

0x401c80 STP	X22, X21, [SP, #64]

0x401c84 STP	X20, X19, [SP, #80]

0x401c88 ADD	X29, SP, #32

0x401c8c ADDVL	SP, SP, #59

0x401c90 FMOV	D23, #2.0000000

0x401c94 FMOV	D0, #3.0000000

0x401c98 MOVZ	W8, #100

0x401c9c HINT	#0

(14) 0x401ca0 FMUL	D1, D23, D0

(14) 0x401ca4 SUBS	W8, W8, #2

(14) 0x401ca8 FADD	D2, D23, D1

(14) 0x401cac FMADD	D1, D2, D0, D1

(14) 0x401cb0 FMUL	D22, D1, D0

(14) 0x401cb4 FADD	D21, D1, D22

(14) 0x401cb8 FMADD	D23, D21, D0, D22

(14) 0x401cbc B.NE	401ca0

0x401cc0 RDVL	X12, #1

0x401cc4 ADRP	X10,

0x401cc8 ADD	X10, X10, #184

0x401ccc MOVZ	W13, #13125

0x401cd0 DUP	Z2.D, Z23.D[0]

0x401cd4 DUP	Z3.D, Z22.D[0]

0x401cd8 DUP	Z4.D, Z21.D[0]

0x401cdc PTRUE	P0.B, ALL

0x401ce0 MOVI	D0, #0

0x401ce4 MOVI	D24, #0

0x401ce8 MOVI	D1, #0

0x401cec ORR	X11, XZR, XZR

0x401cf0 LDP	X8, X9, [X10]

0x401cf4 LDR	X10, [X10, #16]

0x401cf8 UBFM	X21, X12, #4, #63

0x401cfc ORR	W12, WZR, #1758

0x401d00 PTRUE	P3.D, ALL

0x401d04 MADD	X12, X21, X12, XZR

0x401d08 RDVL	X19, #2

0x401d0c AND	X12, X12, X13

0x401d10 CNTW	X20, ALL

0x401d14 ORR	X13, XZR, X12

0x401d18 HINT	#0

0x401d1c HINT	#0

(15) 0x401d20 LD1B	{Z5.B}, P0/Z, [X8, X11]

(15) 0x401d24 ADD	X14, X8, X11

(15) 0x401d28 SUBS	X13, X13, X20

(15) 0x401d2c LD1D	{Z6.D}, P3/Z, [X14, #1, MUL VL]

(15) 0x401d30 ADD	X14, X9, X11

(15) 0x401d34 FSUB	Z5.D, Z5.D, Z2.D

(15) 0x401d38 FSUB	Z6.D, Z6.D, Z2.D

(15) 0x401d3c FCMGE	P1.D, P3/Z, Z5.D, #0

(15) 0x401d40 MOVPRFX	Z7, Z5

(15) 0x401d44 FNEG	Z7.D, P3/M, Z5.D

(15) 0x401d48 FCMGE	P2.D, P3/Z, Z6.D, #0

(15) 0x401d4c MOVPRFX	Z16, Z6

(15) 0x401d50 FNEG	Z16.D, P3/M, Z6.D

(15) 0x401d54 EOR	P1.B, P3/Z, P1.B, P3.B

(15) 0x401d58 SEL	Z5.D, P1, Z7.D, Z5.D

(15) 0x401d5c LD1B	{Z7.B}, P0/Z, [X9, X11]

(15) 0x401d60 EOR	P2.B, P3/Z, P2.B, P3.B

(15) 0x401d64 SEL	Z6.D, P2, Z16.D, Z6.D

(15) 0x401d68 LD1D	{Z16.D}, P3/Z, [X14, #1, MUL VL]

(15) 0x401d6c ADD	X14, X10, X11

(15) 0x401d70 FADDA	D0, P3, D0, Z5.D

(15) 0x401d74 FSUB	Z7.D, Z7.D, Z3.D

(15) 0x401d78 FSUB	Z16.D, Z16.D, Z3.D

(15) 0x401d7c FCMGE	P1.D, P3/Z, Z7.D, #0

(15) 0x401d80 MOVPRFX	Z17, Z7

(15) 0x401d84 FNEG	Z17.D, P3/M, Z7.D

(15) 0x401d88 FCMGE	P2.D, P3/Z, Z16.D, #0

(15) 0x401d8c MOVPRFX	Z18, Z16

(15) 0x401d90 FNEG	Z18.D, P3/M, Z16.D

(15) 0x401d94 EOR	P1.B, P3/Z, P1.B, P3.B

(15) 0x401d98 SEL	Z7.D, P1, Z17.D, Z7.D

(15) 0x401d9c LD1B	{Z17.B}, P0/Z, [X10, X11]

(15) 0x401da0 EOR	P2.B, P3/Z, P2.B, P3.B

(15) 0x401da4 FADDA	D0, P3, D0, Z6.D

(15) 0x401da8 ADD	X11, X11, X19

(15) 0x401dac SEL	Z16.D, P2, Z18.D, Z16.D

(15) 0x401db0 LD1D	{Z18.D}, P3/Z, [X14, #1, MUL VL]

(15) 0x401db4 FADDA	D1, P3, D1, Z7.D

(15) 0x401db8 FSUB	Z17.D, Z17.D, Z4.D

(15) 0x401dbc FSUB	Z18.D, Z18.D, Z4.D

(15) 0x401dc0 FCMGE	P1.D, P3/Z, Z17.D, #0

(15) 0x401dc4 MOVPRFX	Z19, Z17

(15) 0x401dc8 FNEG	Z19.D, P3/M, Z17.D

(15) 0x401dcc FCMGE	P2.D, P3/Z, Z18.D, #0

(15) 0x401dd0 MOVPRFX	Z20, Z18

(15) 0x401dd4 FNEG	Z20.D, P3/M, Z18.D

(15) 0x401dd8 EOR	P1.B, P3/Z, P1.B, P3.B

(15) 0x401ddc FADDA	D1, P3, D1, Z16.D

(15) 0x401de0 SEL	Z17.D, P1, Z19.D, Z17.D

(15) 0x401de4 EOR	P2.B, P3/Z, P2.B, P3.B

(15) 0x401de8 SEL	Z5.D, P2, Z20.D, Z18.D

(15) 0x401dec FADDA	D24, P3, D24, Z17.D

(15) 0x401df0 FADDA	D24, P3, D24, Z5.D

(15) 0x401df4 B.NE	401d20

0x401df8 MOVN	X22, #65535

0x401dfc MOVZ	W11, #13125

0x401e00 MOVK	X22, #52411

0x401e04 CMP	X12, X11

0x401e08 B.EQ	401e70

0x401e0c ADD	X11, X12, X22

0x401e10 ADD	X10, X10, X12,LSL #3

0x401e14 ADD	X9, X9, X12,LSL #3

0x401e18 ADD	X8, X8, X12,LSL #3

0x401e1c HINT	#0

(22) 0x401e20 LDR	D2, [X8], #8

(22) 0x401e24 FSUB	D2, D2, S23

(22) 0x401e28 FNEG	D3, D2

(22) 0x401e2c FCMP	D2, #0

(22) 0x401e30 FCSEL	D2, D3, D2, #11

(22) 0x401e34 FADD	D0, D0, D2

(22) 0x401e38 LDR	D2, [X9], #8

(22) 0x401e3c FSUB	D2, D2, S22

(22) 0x401e40 FNEG	D3, D2

(22) 0x401e44 FCMP	D2, #0

(22) 0x401e48 FCSEL	D2, D3, D2, #11

(22) 0x401e4c FADD	D1, D1, D2

(22) 0x401e50 LDR	D2, [X10], #8

(22) 0x401e54 FSUB	D2, D2, S21

(22) 0x401e58 FNEG	D3, D2

(22) 0x401e5c FCMP	D2, #0

(22) 0x401e60 FCSEL	D2, D3, D2, #11

(22) 0x401e64 ADDS	X11, X11, #1

(22) 0x401e68 FADD	D24, D24, D2

(22) 0x401e6c B.CC	401e20

0x401e70 MOVZ	X8, #41600

0x401e74 MOVK	X8, #16841

0x401e78 FMOV	D11, X8

0x401e7c ADRP	X8,

0x401e80 LDR	D2, [X8, #936]

0x401e84 SUB	X8, X29, #32

0x401e88 STR	Z21, [X8, #510, MUL VL]

0x401e8c STR	Z22, [X8, #509, MUL VL]

0x401e90 FDIV	D8, D0, D11

0x401e94 FDIV	D9, D1, D11

0x401e98 STR	Z2, [X8, #511, MUL VL]

0x401e9c FDIV	D0, D8, D23

0x401ea0 FNEG	D1, D0

0x401ea4 FCMP	D0, #0

0x401ea8 FCSEL	D10, D1, D0, #11

0x401eac FCMP	D10, D2

0x401eb0 B.LE	402008

0x401eb4 FMOV	D0, D2

0x401eb8 ADRP	X0,

0x401ebc ADD	X0, X0, #2992

0x401ec0 STR	Z24, [X8, #507, MUL VL]

0x401ec4 STR	Z23, [X8, #508, MUL VL]

0x401ec8 BL	400960

0x401ecc SUB	X8, X29, #32

0x401ed0 FNEG	D0, D8

0x401ed4 FCMP	D8, #0

0x401ed8 ADRP	X0,

0x401edc ADD	X0, X0, #3053

0x401ee0 LDR	Z1, [X8, #508, MUL VL]

0x401ee4 FCSEL	D0, D8, D0, #10

0x401ee8 FDIV	D2, D0, D1

0x401eec FMOV	D1, D8

0x401ef0 LDR	Z0, [X8, #508, MUL VL]

0x401ef4 BL	400960

0x401ef8 SUB	X8, X29, #32

0x401efc ORR	W9, WZR, #1758

0x401f00 DUP	Z0.D, #0

0x401f04 MOVZ	W10, #13125

0x401f08 FDUP	Z2.D, #240

0x401f0c PTRUE	P2.D, ALL

0x401f10 LDR	Z19, [X8, #508, MUL VL]

0x401f14 LDR	Z18, [X8, #511, MUL VL]

0x401f18 ADRP	X8,

0x401f1c MADD	X9, X21, X9, XZR

0x401f20 DUP	Z4.D, #1

0x401f24 LDR	X8, [X8, #184]

0x401f28 ORR	Z5.D, Z0.D, Z0.D

0x401f2c AND	X9, X9, X10

0x401f30 ORR	X10, XZR, X9

0x401f34 ORR	X11, XZR, X8

0x401f38 DUP	Z1.D, Z19.D[0]

0x401f3c DUP	Z3.D, Z18.D[0]

(20) 0x401f40 LD1D	{Z6.D}, P2/Z, [X11, MUL VL]

(20) 0x401f44 LD1D	{Z7.D}, P2/Z, [X11, #1, MUL VL]

(20) 0x401f48 SUBS	X10, X10, X20

(20) 0x401f4c ADD	X11, X11, X19

(20) 0x401f50 FDIV	Z6.D, P2/M, Z6.D, Z1.D

(20) 0x401f54 FADD	Z6.D, Z6.D, Z2.D

(20) 0x401f58 FDIV	Z7.D, P2/M, Z7.D, Z1.D

(20) 0x401f5c FADD	Z7.D, Z7.D, Z2.D

(20) 0x401f60 FCMGE	P0.D, P2/Z, Z6.D, #0

(20) 0x401f64 FCMGE	P1.D, P2/Z, Z7.D, #0

(20) 0x401f68 MOVPRFX	Z16, Z6

(20) 0x401f6c FNEG	Z16.D, P2/M, Z6.D

(20) 0x401f70 MOVPRFX	Z17, Z7

(20) 0x401f74 FNEG	Z17.D, P2/M, Z7.D

(20) 0x401f78 EOR	P0.B, P2/Z, P0.B, P2.B

(20) 0x401f7c EOR	P1.B, P2/Z, P1.B, P2.B

(20) 0x401f80 SEL	Z6.D, P0, Z16.D, Z6.D

(20) 0x401f84 SEL	Z7.D, P1, Z17.D, Z7.D

(20) 0x401f88 FCMGT	P0.D, P2/Z, Z6.D, Z3.D

(20) 0x401f8c FCMGT	P1.D, P2/Z, Z7.D, Z3.D

(20) 0x401f90 ADD	Z0.D, P0/M, Z0.D, Z4.D

(20) 0x401f94 ADD	Z5.D, P1/M, Z5.D, Z4.D

(20) 0x401f98 B.NE	401f40

0x401f9c ADD	Z0.D, Z5.D, Z0.D

0x401fa0 MOVZ	W10, #13125

0x401fa4 CMP	X9, X10

0x401fa8 UADDV	D0, P2, Z0.D

0x401fac FMOV	X1, D0

0x401fb0 B.EQ	401fe8

0x401fb4 FMOV	D0, #-1.0000000

0x401fb8 ADD	X10, X9, X22

0x401fbc ADD	X8, X8, X9,LSL #3

(21) 0x401fc0 LDR	D1, [X8], #8

(21) 0x401fc4 FDIV	D1, D1, D19

(21) 0x401fc8 FADD	D1, D1, D0

(21) 0x401fcc FNEG	D2, D1

(21) 0x401fd0 FCMP	D1, #0

(21) 0x401fd4 FCSEL	D1, D2, D1, #11

(21) 0x401fd8 FCMP	D1, D18

(21) 0x401fdc CSINC	W1, W1, W1, #13

(21) 0x401fe0 ADDS	X10, X10, #1

(21) 0x401fe4 B.CC	401fc0

0x401fe8 ADRP	X0,

0x401fec ADD	X0, X0, #3111

0x401ff0 BL	400960

0x401ff4 SUB	X8, X29, #32

0x401ff8 LDR	Z2, [X8, #511, MUL VL]

0x401ffc LDR	Z21, [X8, #510, MUL VL]

0x402000 LDR	Z22, [X8, #509, MUL VL]

0x402004 LDR	Z24, [X8, #507, MUL VL]

0x402008 FDIV	D0, D9, D22

0x40200c FNEG	D1, D0

0x402010 FDIV	D8, D24, D11

0x402014 FCMP	D0, #0

0x402018 FCSEL	D0, D1, D0, #11

0x40201c FCMP	D0, D2

0x402020 B.LE	40219c

0x402024 FMOV	D0, D2

0x402028 ADRP	X0, 402028

0x40202c ADD	X0, X0, #3154

0x402030 BL	400960

0x402034 SUB	X8, X29, #32

0x402038 FNEG	D0, D9

0x40203c FCMP	D9, #0

0x402040 ADRP	X0, 402040

0x402044 ADD	X0, X0, #3053

0x402048 LDR	Z1, [X8, #509, MUL VL]

0x40204c FCSEL	D0, D9, D0, #10

0x402050 FDIV	D2, D0, D1

0x402054 FMOV	D1, D9

0x402058 LDR	Z0, [X8, #509, MUL VL]

0x40205c BL	400960

0x402060 ADRP	X0, 402060

0x402064 ADD	X0, X0, #3215

0x402068 SUB	X8, X29, #32

0x40206c LDR	Z0, [X8, #511, MUL VL]

0x402070 BL	400960

0x402074 SUB	X8, X29, #32

0x402078 ORR	W9, WZR, #1758

0x40207c DUP	Z0.D, #0

0x402080 MOVZ	W10, #13125

0x402084 FDUP	Z2.D, #240

0x402088 PTRUE	P2.D, ALL

0x40208c LDR	Z19, [X8, #511, MUL VL]

0x402090 LDR	Z18, [X8, #509, MUL VL]

0x402094 ADRP	X8,

0x402098 MADD	X9, X21, X9, XZR

0x40209c DUP	Z4.D, #1

0x4020a0 LDR	X8, [X8, #192]

0x4020a4 ORR	Z5.D, Z0.D, Z0.D

0x4020a8 AND	X9, X9, X10

0x4020ac ORR	X10, XZR, X9

0x4020b0 ORR	X11, XZR, X8

0x4020b4 DUP	Z1.D, Z18.D[0]

0x4020b8 DUP	Z3.D, Z19.D[0]

0x4020bc HINT	#0

(18) 0x4020c0 LD1D	{Z6.D}, P2/Z, [X11, MUL VL]

(18) 0x4020c4 LD1D	{Z7.D}, P2/Z, [X11, #1, MUL VL]

(18) 0x4020c8 SUBS	X10, X10, X20

(18) 0x4020cc ADD	X11, X11, X19

(18) 0x4020d0 FDIV	Z6.D, P2/M, Z6.D, Z1.D

(18) 0x4020d4 FADD	Z6.D, Z6.D, Z2.D

(18) 0x4020d8 FDIV	Z7.D, P2/M, Z7.D, Z1.D

(18) 0x4020dc FADD	Z7.D, Z7.D, Z2.D

(18) 0x4020e0 FCMGE	P0.D, P2/Z, Z6.D, #0

(18) 0x4020e4 FCMGE	P1.D, P2/Z, Z7.D, #0

(18) 0x4020e8 MOVPRFX	Z16, Z6

(18) 0x4020ec FNEG	Z16.D, P2/M, Z6.D

(18) 0x4020f0 MOVPRFX	Z17, Z7

(18) 0x4020f4 FNEG	Z17.D, P2/M, Z7.D

(18) 0x4020f8 EOR	P0.B, P2/Z, P0.B, P2.B

(18) 0x4020fc EOR	P1.B, P2/Z, P1.B, P2.B

(18) 0x402100 SEL	Z6.D, P0, Z16.D, Z6.D

(18) 0x402104 SEL	Z7.D, P1, Z17.D, Z7.D

(18) 0x402108 FCMGT	P0.D, P2/Z, Z6.D, Z3.D

(18) 0x40210c FCMGT	P1.D, P2/Z, Z7.D, Z3.D

(18) 0x402110 ADD	Z0.D, P0/M, Z0.D, Z4.D

(18) 0x402114 ADD	Z5.D, P1/M, Z5.D, Z4.D

(18) 0x402118 B.NE	4020c0

0x40211c ADD	Z0.D, Z5.D, Z0.D

0x402120 MOVZ	W10, #13125

0x402124 CMP	X9, X10

0x402128 UADDV	D0, P2, Z0.D

0x40212c FMOV	X1, D0

0x402130 B.EQ	402168

0x402134 FMOV	D0, #-1.0000000

0x402138 ADD	X10, X9, X22

0x40213c ADD	X8, X8, X9,LSL #3

(19) 0x402140 LDR	D1, [X8], #8

(19) 0x402144 FDIV	D1, D1, D18

(19) 0x402148 FADD	D1, D1, D0

(19) 0x40214c FNEG	D2, D1

(19) 0x402150 FCMP	D1, #0

(19) 0x402154 FCSEL	D1, D2, D1, #11

(19) 0x402158 FCMP	D1, D19

(19) 0x40215c CSINC	W1, W1, W1, #13

(19) 0x402160 ADDS	X10, X10, #1

(19) 0x402164 B.CC	402140

0x402168 ADRP	X0, 402168

0x40216c ADD	X0, X0, #3249

0x402170 BL	400960

0x402174 SUB	X8, X29, #32

0x402178 LDR	Z0, [X8, #510, MUL VL]

0x40217c LDR	Z2, [X8, #511, MUL VL]

0x402180 FDIV	D0, D8, D0

0x402184 FNEG	D1, D0

0x402188 FCMP	D0, #0

0x40218c FCSEL	D0, D1, D0, #11

0x402190 FCMP	D0, D2

0x402194 B.GT	4021b4

0x402198 B	402350

0x40219c FDIV	D0, D8, D21

0x4021a0 FNEG	D1, D0

0x4021a4 FCMP	D0, #0

0x4021a8 FCSEL	D0, D1, D0, #11

0x4021ac FCMP	D0, D2

0x4021b0 B.LE	40231c

0x4021b4 FMOV	D0, D2

0x4021b8 ADRP	X0, 4021b8

0x4021bc ADD	X0, X0, #3292

0x4021c0 BL	400960

0x4021c4 SUB	X8, X29, #32

0x4021c8 FNEG	D0, D8

0x4021cc FCMP	D8, #0

0x4021d0 ADRP	X0, 4021d0

0x4021d4 ADD	X0, X0, #3053

0x4021d8 LDR	Z1, [X8, #510, MUL VL]

0x4021dc FCSEL	D0, D8, D0, #10

0x4021e0 FDIV	D2, D0, D1

0x4021e4 FMOV	D1, D8

0x4021e8 LDR	Z0, [X8, #510, MUL VL]

0x4021ec BL	400960

0x4021f0 ADRP	X0, 4021f0

0x4021f4 ADD	X0, X0, #3215

0x4021f8 SUB	X8, X29, #32

0x4021fc LDR	Z0, [X8, #511, MUL VL]

0x402200 BL	400960

0x402204 SUB	X8, X29, #32

0x402208 ORR	W9, WZR, #1758

0x40220c DUP	Z0.D, #0

0x402210 MOVZ	W10, #13125

0x402214 FDUP	Z2.D, #240

0x402218 PTRUE	P2.D, ALL

0x40221c LDR	Z19, [X8, #511, MUL VL]

0x402220 LDR	Z18, [X8, #510, MUL VL]

0x402224 ADRP	X8,

0x402228 MADD	X9, X21, X9, XZR

0x40222c DUP	Z4.D, #1

0x402230 LDR	X8, [X8, #200]

0x402234 ORR	Z5.D, Z0.D, Z0.D

0x402238 AND	X9, X9, X10

0x40223c ORR	X10, XZR, X9

0x402240 ORR	X11, XZR, X8

0x402244 DUP	Z1.D, Z18.D[0]

0x402248 DUP	Z3.D, Z19.D[0]

(16) 0x40224c LD1D	{Z6.D}, P2/Z, [X11, MUL VL]

(16) 0x402250 LD1D	{Z7.D}, P2/Z, [X11, #1, MUL VL]

(16) 0x402254 SUBS	X10, X10, X20

(16) 0x402258 ADD	X11, X11, X19

(16) 0x40225c FDIV	Z6.D, P2/M, Z6.D, Z1.D

(16) 0x402260 FADD	Z6.D, Z6.D, Z2.D

(16) 0x402264 FDIV	Z7.D, P2/M, Z7.D, Z1.D

(16) 0x402268 FADD	Z7.D, Z7.D, Z2.D

(16) 0x40226c FCMGE	P0.D, P2/Z, Z6.D, #0

(16) 0x402270 FCMGE	P1.D, P2/Z, Z7.D, #0

(16) 0x402274 MOVPRFX	Z16, Z6

(16) 0x402278 FNEG	Z16.D, P2/M, Z6.D

(16) 0x40227c MOVPRFX	Z17, Z7

(16) 0x402280 FNEG	Z17.D, P2/M, Z7.D

(16) 0x402284 EOR	P0.B, P2/Z, P0.B, P2.B

(16) 0x402288 EOR	P1.B, P2/Z, P1.B, P2.B

(16) 0x40228c SEL	Z6.D, P0, Z16.D, Z6.D

(16) 0x402290 SEL	Z7.D, P1, Z17.D, Z7.D

(16) 0x402294 FCMGT	P0.D, P2/Z, Z6.D, Z3.D

(16) 0x402298 FCMGT	P1.D, P2/Z, Z7.D, Z3.D

(16) 0x40229c ADD	Z0.D, P0/M, Z0.D, Z4.D

(16) 0x4022a0 ADD	Z5.D, P1/M, Z5.D, Z4.D

(16) 0x4022a4 B.NE	40224c

0x4022a8 ADD	Z0.D, Z5.D, Z0.D

0x4022ac MOVZ	W10, #13125

0x4022b0 CMP	X9, X10

0x4022b4 UADDV	D0, P2, Z0.D

0x4022b8 FMOV	X1, D0

0x4022bc B.EQ	4022f4

0x4022c0 FMOV	D0, #-1.0000000

0x4022c4 ADD	X10, X9, X22

0x4022c8 ADD	X8, X8, X9,LSL #3

(17) 0x4022cc LDR	D1, [X8], #8

(17) 0x4022d0 FDIV	D1, D1, D18

(17) 0x4022d4 FADD	D1, D1, D0

(17) 0x4022d8 FNEG	D2, D1

(17) 0x4022dc FCMP	D1, #0

(17) 0x4022e0 FCSEL	D1, D2, D1, #11

(17) 0x4022e4 FCMP	D1, D19

(17) 0x4022e8 CSINC	W1, W1, W1, #13

(17) 0x4022ec ADDS	X10, X10, #1

(17) 0x4022f0 B.CC	4022cc

0x4022f4 ADRP	X0, 4022f4

0x4022f8 ADD	X0, X0, #3353

0x4022fc ADDVL	SP, SP, #5

0x402300 LDP	D9, D8, [SP, #16]

0x402304 LDP	X20, X19, [SP, #80]

0x402308 LDR	X28, [SP, #48]

0x40230c LDP	X22, X21, [SP, #64]

0x402310 LDP	X29, X30, [SP, #32]

0x402314 LDP	D11, D10, [SP], #96

0x402318 B	400960

0x40231c FCMP	D10, D2

0x402320 B.GT	402350

0x402324 ADRP	X0, 402324

0x402328 ADD	X0, X0, #3396

0x40232c FMOV	D0, D2

0x402330 ADDVL	SP, SP, #5

0x402334 LDP	D9, D8, [SP, #16]

0x402338 LDP	X20, X19, [SP, #80]

0x40233c LDR	X28, [SP, #48]

0x402340 LDP	X22, X21, [SP, #64]

0x402344 LDP	X29, X30, [SP, #32]

0x402348 LDP	D11, D10, [SP], #96

0x40234c B	400960

0x402350 ADDVL	SP, SP, #5

0x402354 LDP	D9, D8, [SP, #16]

0x402358 LDP	X20, X19, [SP, #80]

0x40235c LDR	X28, [SP, #48]

0x402360 LDP	X22, X21, [SP, #64]

0x402364 LDP	X29, X30, [SP, #32]

0x402368 LDP	D11, D10, [SP], #96

0x40236c RET

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:394	exec
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:456-571
Module	exec

The function is defined in /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:456,472-477,484-491,506-512,522-531,541-550,560-563,571.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 34.97 to 13.50 cycles (2.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 44% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 34.97 to 21.59 cycles (1.62x speedup).

Details

26% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
63% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
12% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 34.97 to 5.00 cycles (6.99x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 10 occurrences►
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:508
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:509
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:522
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:526
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:527
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:528
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:541
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:545
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:546
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:547

Matching between your function (in the source code) and the binary function

The binary function is composed of 10 FP arithmetical operations:

10: divide

The binary function is loading 960 bytes. The binary function is storing 248 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	267
nb uops	259
loop length	1068
used w registers	7
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	11
used q registers	0
used v registers	0
used z registers	12
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.38 cycles
front end	32.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	29.00	29.00	29.00	29.00	24.00	24.00	19.00	19.00	18.50	18.17	18.33	2.00	2.00
cycles	11.50	11.50	29.00	29.00	29.00	29.00	24.00	24.00	19.00	19.00	18.50	18.17	18.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

17.51-34.97

Cycles summary

Front-end	32.38
Dispatch	29.00
DIV/SQRT	17.51-34.97
Overall L1	32.38-34.97

Vectorization ratios

INT

all	36%
load	66%
store	63%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	0%
other	23%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	26%
load	66%
store	63%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	0%
div/sqrt	0%
other	12%

Vector efficiency ratios

INT

all	53%
load	73%
store	70%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	38%
fma	25%
other	45%

all	23%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	23%

INT+FP

all	44%
load	73%
store	70%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	38%
fma	25%
div/sqrt	25%
other	35%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.97 cycles. At this rate:

28% of peak load performance is reached (27.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 401c70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D11, D10, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X28, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADDVL SP, SP, #59	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMOV D23, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D0, #3.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ W8, #100	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
RDVL X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X10, <420cc4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W13, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z2.D, Z23.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z22.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z21.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D24, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X8, X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X12, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W12, WZR, #1758	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P3.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MADD X12, X21, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
RDVL X19, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTW X20, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ORR X13, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
MOVN X22, #65535	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W11, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK X22, #52411	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401e70 <checkSTREAMresults+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X12, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X8, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
MOVZ X8, #41600	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X8, #16841	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D11, X8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADRP X8, <402e7c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X8, #936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z21, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z22, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FDIV D8, D0, D11	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FDIV D9, D1, D11	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
STR Z2, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FDIV D0, D8, D23	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D10, D1, D0, #11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D10, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 402008 <checkSTREAMresults+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADRP X0, <402eb8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2992	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR Z24, [X8, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z23, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FNEG D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D8, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X0, <402ed8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3053	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR Z1, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCSEL D0, D8, D0, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMOV D1, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Z0, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, #1758	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR Z19, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z18, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
ADRP X8, <420f18>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X21, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
LDR X8, [X8, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
AND X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z1.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z18.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UADDV D0, P2, Z0.D																			vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 401fe8 <checkSTREAMresults+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X10, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <402fe8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3111	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z2, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z21, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z22, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z24, [X8, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FDIV D0, D9, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDIV D8, D24, D11	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 40219c <checkSTREAMresults+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADRP X0, 402028 <checkSTREAMresults+0x3b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3154	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FNEG D0, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D9, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X0, 402040 <checkSTREAMresults+0x3d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3053	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR Z1, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCSEL D0, D9, D0, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMOV D1, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Z0, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, 402060 <checkSTREAMresults+0x3f0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3215	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, #1758	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR Z19, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z18, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
ADRP X8, <420094>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X21, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
LDR X8, [X8, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
AND X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z1.D, Z18.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
HINT #0																			N/A
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UADDV D0, P2, Z0.D																			vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 402168 <checkSTREAMresults+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X10, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, 402168 <checkSTREAMresults+0x4f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z0, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z2, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FDIV D0, D8, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4021b4 <checkSTREAMresults+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 402350 <checkSTREAMresults+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D0, D8, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 40231c <checkSTREAMresults+0x6ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADRP X0, 4021b8 <checkSTREAMresults+0x548>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3292	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FNEG D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D8, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X0, 4021d0 <checkSTREAMresults+0x560>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3053	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR Z1, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCSEL D0, D8, D0, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMOV D1, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Z0, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, 4021f0 <checkSTREAMresults+0x580>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3215	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, #1758	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR Z19, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z18, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
ADRP X8, <420224>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X21, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
LDR X8, [X8, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
AND X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z1.D, Z18.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UADDV D0, P2, Z0.D																			vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 4022f4 <checkSTREAMresults+0x684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X10, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, 4022f4 <checkSTREAMresults+0x684>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3353	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADDVL SP, SP, #5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X28, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D10, [SP], #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 400960 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D10, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 402350 <checkSTREAMresults+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, 402324 <checkSTREAMresults+0x6b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3396	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADDVL SP, SP, #5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X28, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D10, [SP], #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 400960 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X28, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D10, [SP], #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:456-571
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

26% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
63% of VPU stores are used in vector version.
18% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
12% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 34.97 to 5.00 cycles (6.99x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 10 occurrences►
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:508
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:509
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:522
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:526
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:527
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:528
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:541
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:545
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:546
- /home/eoseret/Tools/QaaS/qaas_runs/175-491-9774/intel/stream/build/stream/src/stream.c:547

Matching between your function (in the source code) and the binary function

The binary function is composed of 10 FP arithmetical operations:

10: divide

The binary function is loading 960 bytes. The binary function is storing 248 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	267
nb uops	259
loop length	1068
used w registers	7
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	11
used q registers	0
used v registers	0
used z registers	12
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.38 cycles
front end	32.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	29.00	29.00	29.00	29.00	24.00	24.00	19.00	19.00	18.50	18.17	18.33	2.00	2.00
cycles	11.50	11.50	29.00	29.00	29.00	29.00	24.00	24.00	19.00	19.00	18.50	18.17	18.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

17.51-34.97

Cycles summary

Front-end	32.38
Dispatch	29.00
DIV/SQRT	17.51-34.97
Overall L1	32.38-34.97

Vectorization ratios

INT

all	36%
load	66%
store	63%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	0%
other	23%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	26%
load	66%
store	63%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	0%
div/sqrt	0%
other	12%

Vector efficiency ratios

INT

all	53%
load	73%
store	70%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	38%
fma	25%
other	45%

all	23%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	23%

INT+FP

all	44%
load	73%
store	70%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	38%
fma	25%
div/sqrt	25%
other	35%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.97 cycles. At this rate:

28% of peak load performance is reached (27.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 401c70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D11, D10, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X28, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADDVL SP, SP, #59	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMOV D23, #2.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D0, #3.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVZ W8, #100	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
RDVL X12, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X10, <420cc4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W13, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z2.D, Z23.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z22.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z21.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D24, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X8, X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X21, X12, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W12, WZR, #1758	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P3.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MADD X12, X21, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
RDVL X19, #2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTW X20, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ORR X13, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
MOVN X22, #65535	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W11, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVK X22, #52411	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 401e70 <checkSTREAMresults+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X12, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X8, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
MOVZ X8, #41600	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X8, #16841	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D11, X8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADRP X8, <402e7c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D2, [X8, #936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z21, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z22, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FDIV D8, D0, D11	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FDIV D9, D1, D11	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
STR Z2, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FDIV D0, D8, D23	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D10, D1, D0, #11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D10, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 402008 <checkSTREAMresults+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADRP X0, <402eb8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #2992	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR Z24, [X8, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z23, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FNEG D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D8, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X0, <402ed8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3053	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR Z1, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCSEL D0, D8, D0, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMOV D1, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Z0, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, #1758	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR Z19, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z18, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
ADRP X8, <420f18>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X21, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
LDR X8, [X8, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
AND X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z1.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z18.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UADDV D0, P2, Z0.D																			vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 401fe8 <checkSTREAMresults+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X10, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <402fe8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3111	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z2, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z21, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z22, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z24, [X8, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FDIV D0, D9, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDIV D8, D24, D11	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 40219c <checkSTREAMresults+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADRP X0, 402028 <checkSTREAMresults+0x3b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3154	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FNEG D0, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D9, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X0, 402040 <checkSTREAMresults+0x3d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3053	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR Z1, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCSEL D0, D9, D0, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMOV D1, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Z0, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, 402060 <checkSTREAMresults+0x3f0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3215	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, #1758	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR Z19, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z18, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
ADRP X8, <420094>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X21, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
LDR X8, [X8, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
AND X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z1.D, Z18.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
HINT #0																			N/A
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UADDV D0, P2, Z0.D																			vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 402168 <checkSTREAMresults+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X10, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, 402168 <checkSTREAMresults+0x4f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z0, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z2, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FDIV D0, D8, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 4021b4 <checkSTREAMresults+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 402350 <checkSTREAMresults+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D0, D8, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FNEG D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D0, D1, D0, #11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LE 40231c <checkSTREAMresults+0x6ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADRP X0, 4021b8 <checkSTREAMresults+0x548>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3292	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FNEG D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D8, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X0, 4021d0 <checkSTREAMresults+0x560>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3053	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR Z1, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FCSEL D0, D8, D0, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
FDIV D2, D0, D1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMOV D1, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR Z0, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, 4021f0 <checkSTREAMresults+0x580>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3215	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
BL 400960 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W9, WZR, #1758	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z2.D, #240	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
PTRUE P2.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR Z19, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z18, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
ADRP X8, <420224>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X21, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
DUP Z4.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
LDR X8, [X8, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR Z5.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
AND X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z1.D, Z18.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z19.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
MOVZ W10, #13125	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UADDV D0, P2, Z0.D																			vect (100.0%)
FMOV X1, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 4022f4 <checkSTREAMresults+0x684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X10, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, 4022f4 <checkSTREAMresults+0x684>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3353	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADDVL SP, SP, #5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X28, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D10, [SP], #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 400960 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D10, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GT 402350 <checkSTREAMresults+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, 402324 <checkSTREAMresults+0x6b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3396	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADDVL SP, SP, #5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X28, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D10, [SP], #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
B 400960 <@plt_start@+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X28, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D11, D10, [SP], #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼checkSTREAMresults–	0.07	0.02
○Loop 15 - stream.c:484-487 - exec	0.07	1.29
○Loop 14 - stream.c:472-477 - exec	0.00	0.00
○Loop 22 - stream.c:484-487 - exec	0.00	0.00
○Loop 18 - stream.c:530-531 - exec	0.00	0.00
○Loop 17 - stream.c:549-550 - exec	0.00	0.00
○Loop 21 - stream.c:511-512 - exec	0.00	0.00
○Loop 16 - stream.c:549-550 - exec	0.00	0.00
○Loop 20 - stream.c:511-512 - exec	0.00	0.00
○Loop 19 - stream.c:530-531 - exec	0.00	0.00

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Code clean check

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Vectorization

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Expensive FP math instructions/calls

CALL instructions

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Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code