OV - exec - Function main._omp

	Function: main._omp_fn.4	Module: exec	Source: stream.c:354-356	Coverage (incl. loops): 95.64% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c: 354 - 356

--------------------------------------------------------------------------------

354: #pragma omp parallel for

355: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

356: 	    a[j] = b[j]+scalar*c[j];

0x402100 PUSH	%RBP

0x402101 MOV	$0x401060,%RAX

0x40210b MOV	%RSP,%RBP

0x40210e PUSH	%R14

0x402110 PUSH	%R13

0x402112 MOV	$0x401030,%R13

0x40211c PUSH	%R12

0x40211e PUSH	%RBX

0x40211f MOV	%RDI,%RBX

0x402122 AND	$-0x40,%RSP

0x402126 CALL	%RAX

0x402128 MOVSXD	%EAX,%R12

0x40212b CALL	%R13

0x40212e MOVSXD	%EAX,%RCX

0x402131 MOV	$0x33450000,%EAX

0x402136 CQTO

0x402138 IDIV	%R12

0x40213b CMP	%RDX,%RCX

0x40213e JL	402430

0x402144 IMUL	%RAX,%RCX

0x402148 ADD	%RCX,%RDX

0x40214b LEA	(%RAX,%RDX,1),%R11

0x40214f CMP	%R11,%RDX

0x402152 JGE	40240d

0x402158 LEA	-0x1(%RAX),%RSI

0x40215c VMOVSD	(%RBX),%XMM1

0x402160 MOV	%RDX,%R14

0x402163 CMP	$0x6,%RSI

0x402167 JBE	402440

0x40216d MOV	%RAX,%R10

0x402170 SHR	$0x3,%R10

0x402174 SAL	$0x6,%R10

0x402178 LEA	-0x40(%R10),%R9

0x40217c SHR	$0x6,%R9

0x402180 LEA	(,%RDX,8),%RSI

0x402188 MOV	$0x19a686100,%R12

0x402192 MOV	$0x406100,%R13

0x40219c MOV	$0x334906100,%RBX

0x4021a6 INC	%R9

0x4021a9 LEA	(%R12,%RSI,1),%RDI

0x4021ad LEA	(%R13,%RSI,1),%R8

0x4021b2 VBROADCASTSD	%XMM1,%ZMM0

0x4021b8 ADD	%RBX,%RSI

0x4021bb XOR	%ECX,%ECX

0x4021bd AND	$0x7,%R9D

0x4021c1 JE	4022a9

0x4021c7 CMP	$0x1,%R9

0x4021cb JE	402287

0x4021d1 CMP	$0x2,%R9

0x4021d5 JE	40226e

0x4021db CMP	$0x3,%R9

0x4021df JE	402255

0x4021e1 CMP	$0x4,%R9

0x4021e5 JE	40223c

0x4021e7 CMP	$0x5,%R9

0x4021eb JE	402223

0x4021ed CMP	$0x6,%R9

0x4021f1 JE	40220a

0x4021f3 VMOVUPD	(%R8),%ZMM2

0x4021f9 MOV	$0x40,%ECX

0x4021fe VFMADD213PD	(%RDI),%ZMM0,%ZMM2

0x402204 VMOVUPD	%ZMM2,(%RSI)

0x40220a VMOVUPD	(%R8,%RCX,1),%ZMM3

0x402211 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM3

0x402218 VMOVUPD	%ZMM3,(%RSI,%RCX,1)

0x40221f ADD	$0x40,%RCX

0x402223 VMOVUPD	(%R8,%RCX,1),%ZMM4

0x40222a VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM4

0x402231 VMOVUPD	%ZMM4,(%RSI,%RCX,1)

0x402238 ADD	$0x40,%RCX

0x40223c VMOVUPD	(%R8,%RCX,1),%ZMM5

0x402243 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM5

0x40224a VMOVUPD	%ZMM5,(%RSI,%RCX,1)

0x402251 ADD	$0x40,%RCX

0x402255 VMOVUPD	(%R8,%RCX,1),%ZMM6

0x40225c VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM6

0x402263 VMOVUPD	%ZMM6,(%RSI,%RCX,1)

0x40226a ADD	$0x40,%RCX

0x40226e VMOVUPD	(%R8,%RCX,1),%ZMM7

0x402275 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM7

0x40227c VMOVUPD	%ZMM7,(%RSI,%RCX,1)

0x402283 ADD	$0x40,%RCX

0x402287 VMOVUPD	(%R8,%RCX,1),%ZMM8

0x40228e VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM8

0x402295 VMOVUPD	%ZMM8,(%RSI,%RCX,1)

0x40229c ADD	$0x40,%RCX

0x4022a0 CMP	%R10,%RCX

0x4022a3 JE	402376

(2) 0x4022a9 VMOVUPD	(%R8,%RCX,1),%ZMM9

(2) 0x4022b0 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM9

(2) 0x4022b7 VMOVUPD	%ZMM9,(%RSI,%RCX,1)

(2) 0x4022be VMOVUPD	0x40(%R8,%RCX,1),%ZMM10

(2) 0x4022c6 VFMADD213PD	0x40(%RDI,%RCX,1),%ZMM0,%ZMM10

(2) 0x4022ce VMOVUPD	%ZMM10,0x40(%RSI,%RCX,1)

(2) 0x4022d6 VMOVUPD	0x80(%R8,%RCX,1),%ZMM11

(2) 0x4022de VFMADD213PD	0x80(%RDI,%RCX,1),%ZMM0,%ZMM11

(2) 0x4022e6 VMOVUPD	%ZMM11,0x80(%RSI,%RCX,1)

(2) 0x4022ee VMOVUPD	0xc0(%R8,%RCX,1),%ZMM12

(2) 0x4022f6 VFMADD213PD	0xc0(%RDI,%RCX,1),%ZMM0,%ZMM12

(2) 0x4022fe VMOVUPD	%ZMM12,0xc0(%RSI,%RCX,1)

(2) 0x402306 VMOVUPD	0x100(%R8,%RCX,1),%ZMM13

(2) 0x40230e VFMADD213PD	0x100(%RDI,%RCX,1),%ZMM0,%ZMM13

(2) 0x402316 VMOVUPD	%ZMM13,0x100(%RSI,%RCX,1)

(2) 0x40231e VMOVUPD	0x140(%R8,%RCX,1),%ZMM14

(2) 0x402326 VFMADD213PD	0x140(%RDI,%RCX,1),%ZMM0,%ZMM14

(2) 0x40232e VMOVUPD	%ZMM14,0x140(%RSI,%RCX,1)

(2) 0x402336 VMOVUPD	0x180(%R8,%RCX,1),%ZMM15

(2) 0x40233e VFMADD213PD	0x180(%RDI,%RCX,1),%ZMM0,%ZMM15

(2) 0x402346 VMOVUPD	%ZMM15,0x180(%RSI,%RCX,1)

(2) 0x40234e VMOVUPD	0x1c0(%R8,%RCX,1),%ZMM2

(2) 0x402356 VFMADD213PD	0x1c0(%RDI,%RCX,1),%ZMM0,%ZMM2

(2) 0x40235e VMOVUPD	%ZMM2,0x1c0(%RSI,%RCX,1)

(2) 0x402366 ADD	$0x200,%RCX

(2) 0x40236d CMP	%R10,%RCX

(2) 0x402370 JNE	4022a9

0x402376 MOV	%RAX,%RDI

0x402379 AND	$-0x8,%RDI

0x40237d ADD	%RDI,%RDX

0x402380 CMP	%RDI,%RAX

0x402383 JE	402420

0x402389 SUB	%RDI,%RAX

0x40238c LEA	-0x1(%RAX),%RSI

0x402390 CMP	$0x2,%RSI

0x402394 JBE	4023c2

0x402396 ADD	%R14,%RDI

0x402399 SAL	$0x3,%RDI

0x40239d VMOVUPD	(%R12,%RDI,1),%YMM3

0x4023a3 VBROADCASTSD	%XMM1,%YMM0

0x4023a8 VFMADD132PD	(%R13,%RDI,1),%YMM3,%YMM0

0x4023af MOV	%RAX,%R14

0x4023b2 AND	$-0x4,%R14

0x4023b6 ADD	%R14,%RDX

0x4023b9 VMOVUPD	%YMM0,(%RBX,%RDI,1)

0x4023be TEST	$0x3,%AL

0x4023c0 JE	402420

0x4023c2 VMOVSD	(%R13,%RDX,8),%XMM4

0x4023c9 LEA	0x1(%RDX),%RAX

0x4023cd VFMADD213SD	(%R12,%RDX,8),%XMM1,%XMM4

0x4023d3 VMOVSD	%XMM4,(%RBX,%RDX,8)

0x4023d8 CMP	%RAX,%R11

0x4023db JLE	402420

0x4023dd VMOVSD	(%R13,%RAX,8),%XMM5

0x4023e4 ADD	$0x2,%RDX

0x4023e8 VFMADD213SD	(%R12,%RAX,8),%XMM1,%XMM5

0x4023ee VMOVSD	%XMM5,(%RBX,%RAX,8)

0x4023f3 CMP	%RDX,%R11

0x4023f6 JLE	402420

0x4023f8 VMOVSD	(%R12,%RDX,8),%XMM6

0x4023fe VFMADD132SD	(%R13,%RDX,8),%XMM6,%XMM1

0x402405 VMOVSD	%XMM1,(%RBX,%RDX,8)

0x40240a VZEROUPPER

0x40240d LEA	-0x20(%RBP),%RSP

0x402411 POP	%RBX

0x402412 POP	%R12

0x402414 POP	%R13

0x402416 POP	%R14

0x402418 POP	%RBP

0x402419 RET

0x40241a NOPW	(%RAX,%RAX,1)

0x402420 VZEROUPPER

0x402423 LEA	-0x20(%RBP),%RSP

0x402427 POP	%RBX

0x402428 POP	%R12

0x40242a POP	%R13

0x40242c POP	%R14

0x40242e POP	%RBP

0x40242f RET

0x402430 INC	%RAX

0x402433 XOR	%EDX,%EDX

0x402435 JMP	402144

0x40243a NOPW	(%RAX,%RAX,1)

0x402440 XOR	%EDI,%EDI

0x402442 MOV	$0x19a686100,%R12

0x40244c MOV	$0x406100,%R13

0x402456 MOV	$0x334906100,%RBX

0x402460 JMP	402389

0x402465 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○99.21	gomp_thread_start	team.c:130	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	stream.c:354-356
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354-356.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.00 to 12.00 cycles (2.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 44% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 28.00 to 22.04 cycles (1.27x speedup).

Details

42% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

69% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
72% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 63 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354
VZEROUPPER: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:356

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time). 7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 126 FP arithmetical operations:

63: addition or subtraction (all inside FMA instructions)
63: multiply (all inside FMA instructions)

The binary function is loading 1016 bytes (127 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	150
nb uops	158
loop length	675
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	8
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.00 cycles
front end	28.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.80	15.80	11.67	11.67	9.00	15.90	15.70	9.00	9.00	9.00	15.80	11.67
cycles	15.80	15.80	11.67	11.67	9.00	15.90	15.70	9.00	9.00	9.00	15.80	11.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	28.00
Dispatch	15.90
DIV/SQRT	10.00
Overall L1	28.00

Vectorization ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	66%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	72%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	42%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	72%
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	66%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	71%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	44%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	71%
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.00 cycles. At this rate:

18% of peak load performance is reached (36.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (18.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 28.00 to 15.90 cycles (1.76x speedup).

ASM code

In the binary file, the address of the function is: 402100

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401060,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401030,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
CALL %R13	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x33450000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R12	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 402430 <main._omp_fn.4+0x330>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 40240d <main._omp_fn.4+0x30d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%RBX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x6,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402440 <main._omp_fn.4+0x340>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x6,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x40(%R10),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA (,%RDX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%R12,%RSI,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%RSI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RBX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
JE 4022a9 <main._omp_fn.4+0x1a9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402287 <main._omp_fn.4+0x187>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40226e <main._omp_fn.4+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402255 <main._omp_fn.4+0x155>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40223c <main._omp_fn.4+0x13c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402223 <main._omp_fn.4+0x123>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40220a <main._omp_fn.4+0x10a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%R8),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV $0x40,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VFMADD213PD (%RDI),%ZMM0,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM2,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R8,%RCX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM6,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM8,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402376 <main._omp_fn.4+0x276>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402420 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 4023c2 <main._omp_fn.4+0x2c2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R14,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x3,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VMOVUPD (%R12,%RDI,1),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VFMADD132PD (%R13,%RDI,1),%YMM3,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x4,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD %YMM0,(%RBX,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
TEST $0x3,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 402420 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R13,%RDX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD213SD (%R12,%RDX,8),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM4,(%RBX,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402420 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R13,%RAX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x2,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD (%R12,%RAX,8),%XMM1,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM5,(%RBX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402420 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R12,%RDX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD132SD (%R13,%RDX,8),%XMM6,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%RBX,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 402144 <main._omp_fn.4+0x44>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
JMP 402389 <main._omp_fn.4+0x289>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	stream.c:354-356
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

42% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

69% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
72% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 63 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354
VZEROUPPER: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:356

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 126 FP arithmetical operations:

63: addition or subtraction (all inside FMA instructions)
63: multiply (all inside FMA instructions)

The binary function is loading 1016 bytes (127 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	150
nb uops	158
loop length	675
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	8
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	28.00 cycles
front end	28.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.80	15.80	11.67	11.67	9.00	15.90	15.70	9.00	9.00	9.00	15.80	11.67
cycles	15.80	15.80	11.67	11.67	9.00	15.90	15.70	9.00	9.00	9.00	15.80	11.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	28.00
Dispatch	15.90
DIV/SQRT	10.00
Overall L1	28.00

Vectorization ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	66%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	72%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	42%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	72%
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	66%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	71%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	44%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	71%
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.00 cycles. At this rate:

18% of peak load performance is reached (36.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (18.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402100

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401060,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x401030,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%R12	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
CALL %R13	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x33450000,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R12	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 402430 <main._omp_fn.4+0x330>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R11,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 40240d <main._omp_fn.4+0x30d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%RBX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x6,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 402440 <main._omp_fn.4+0x340>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x6,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x40(%R10),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA (,%RDX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%R12,%RSI,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%RSI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RBX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
JE 4022a9 <main._omp_fn.4+0x1a9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402287 <main._omp_fn.4+0x187>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40226e <main._omp_fn.4+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402255 <main._omp_fn.4+0x155>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40223c <main._omp_fn.4+0x13c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402223 <main._omp_fn.4+0x123>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40220a <main._omp_fn.4+0x10a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%R8),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV $0x40,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VFMADD213PD (%RDI),%ZMM0,%ZMM2	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM2,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD (%R8,%RCX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM4	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM5	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM6	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM6,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD (%R8,%RCX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VMOVUPD %ZMM8,(%RSI,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x40,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402376 <main._omp_fn.4+0x276>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 402420 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x1(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x2,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JBE 4023c2 <main._omp_fn.4+0x2c2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R14,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x3,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VMOVUPD (%R12,%RDI,1),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VFMADD132PD (%R13,%RDI,1),%YMM3,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x4,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD %YMM0,(%RBX,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
TEST $0x3,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 402420 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R13,%RDX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD213SD (%R12,%RDX,8),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM4,(%RBX,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402420 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R13,%RAX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x2,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD (%R12,%RAX,8),%XMM1,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM5,(%RBX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 402420 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R12,%RDX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD132SD (%R13,%RDX,8),%XMM6,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%RBX,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 402144 <main._omp_fn.4+0x44>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x19a686100,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x406100,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x334906100,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
JMP 402389 <main._omp_fn.4+0x289>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.4–	95.64	4.18
○Loop 2 - stream.c:356-356 - exec	95.64	4.14

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