OV - exec - Function main.extracted.50

	Function: main.extracted.50	Module: exec	Source: stream.c:354-356	Coverage (incl. loops): 92.52% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c: 354 - 356

--------------------------------------------------------------------------------

354: #pragma omp parallel for

355: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

356: 	    a[j] = b[j]+scalar*c[j];

0x402e50 PUSH	%RBP

0x402e51 MOV	%RSP,%RBP

0x402e54 PUSH	%R15

0x402e56 PUSH	%R14

0x402e58 PUSH	%RBX

0x402e59 SUB	$0x28,%RSP

0x402e5d MOVL	$0,-0x1c(%RBP)

0x402e64 MOV	(%RDI),%EBX

0x402e66 MOVQ	$0,-0x30(%RBP)

0x402e6e MOVQ	$0x3344ffff,-0x28(%RBP)

0x402e76 MOVQ	$0x1,-0x38(%RBP)

0x402e7e SUB	$0x8,%RSP

0x402e82 LEA	-0x38(%RBP),%RAX

0x402e86 MOV	$0x4ceb87e20,%RDI

0x402e90 MOV	$0x401050,%R10

0x402e9a LEA	-0x1c(%RBP),%RCX

0x402e9e LEA	-0x30(%RBP),%R8

0x402ea2 LEA	-0x28(%RBP),%R9

0x402ea6 MOV	%EBX,%ESI

0x402ea8 MOV	$0x22,%EDX

0x402ead PUSH	$0x1

0x402eaf PUSH	$0x1

0x402eb1 PUSH	%RAX

0x402eb2 CALL	%R10

0x402eb5 ADD	$0x20,%RSP

0x402eb9 MOV	-0x30(%RBP),%R8

0x402ebd MOV	-0x28(%RBP),%RAX

0x402ec1 CMP	%RAX,%R8

0x402ec4 JA	402f7e

0x402eca MOV	%RAX,%R10

0x402ecd SUB	%R8,%R10

0x402ed0 INC	%R10

0x402ed3 MOV	%R10,%RCX

0x402ed6 MOV	$0x334905060,%RDX

0x402ee0 MOV	$0x19a685060,%RSI

0x402eea MOV	$0x4030d0,%R9

0x402ef4 MOV	$0x405060,%RDI

0x402efe AND	$0x7ffffffc,%RCX

0x402f05 JE	402f46

0x402f07 LEA	(,%R8,8),%R11

0x402f0f XOR	%R14D,%R14D

0x402f12 VBROADCASTSD	(%R9),%YMM0

0x402f17 NOPW	(%RAX,%RAX,1)

(16) 0x402f20 LEA	(%R11,%R14,8),%R15

(16) 0x402f24 VMOVUPD	(%RDX,%R15,1),%YMM1

(16) 0x402f2a VFMADD213PD	(%RSI,%R15,1),%YMM0,%YMM1

(16) 0x402f30 VMOVUPD	%YMM1,(%RDI,%R15,1)

(16) 0x402f36 ADD	$0x4,%R14

(16) 0x402f3a CMP	%RCX,%R14

(16) 0x402f3d JB	402f20

0x402f3f CMP	%RCX,%R10

0x402f42 JNE	402f48

0x402f44 JMP	402f7e

0x402f46 XOR	%ECX,%ECX

0x402f48 SUB	%RCX,%RAX

0x402f4b SUB	%R8,%RAX

0x402f4e INC	%RAX

0x402f51 ADD	%R8,%RCX

0x402f54 SAL	$0x3,%RCX

0x402f58 XOR	%R8D,%R8D

0x402f5b VMOVSD	(%R9),%XMM0

(15) 0x402f60 LEA	(%RCX,%R8,8),%R9

(15) 0x402f64 VMOVSD	(%RDX,%R9,1),%XMM1

(15) 0x402f6a VFMADD213SD	(%RSI,%R9,1),%XMM0,%XMM1

(15) 0x402f70 VMOVSD	%XMM1,(%RDI,%R9,1)

(15) 0x402f76 INC	%R8

(15) 0x402f79 CMP	%R8,%RAX

(15) 0x402f7c JNE	402f60

0x402f7e MOV	$0x4ceb87e40,%RDI

0x402f88 MOV	$0x401030,%RAX

0x402f92 MOV	%EBX,%ESI

0x402f94 ADD	$0x28,%RSP

0x402f98 POP	%RBX

0x402f99 POP	%R14

0x402f9b POP	%R15

0x402f9d POP	%RBP

0x402f9e VZEROUPPER

0x402fa1 JMP	%RAX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:354-356
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354-356.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.00 to 1.83 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	64
nb uops	66
loop length	278
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.00 cycles
front end	11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.40	4.40	3.00	3.00	6.00	4.40	4.40	6.00	6.00	6.00	4.40	3.00
cycles	4.40	4.40	3.00	3.00	6.00	4.40	4.40	6.00	6.00	6.00	4.40	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.00
Dispatch	6.00
Overall L1	11.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

INT

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.00 cycles. At this rate:

1% of peak load performance is reached (3.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.00 to 6.00 cycles (1.83x speedup).

ASM code

In the binary file, the address of the function is: 402e50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x1c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x28(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4ceb87e20,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x401050,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
LEA -0x1c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 402f7e <main.extracted.50+0x12e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x334905060,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $0x19a685060,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $0x4030d0,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x405060,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND $0x7ffffffc,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
JE 402f46 <main.extracted.50+0xf6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%R8,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VBROADCASTSD (%R9),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RCX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 402f48 <main.extracted.50+0xf8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 402f7e <main.extracted.50+0x12e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SAL $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R9),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x4ceb87e40,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x401030,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	1.75	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	stream.c:354-356
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.00 to 1.83 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/isix05.benchmarkcenter.megware.com/177-373-7249/stream-triad/build/stream-triad/src/stream.c:354

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	64
nb uops	66
loop length	278
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.00 cycles
front end	11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.40	4.40	3.00	3.00	6.00	4.40	4.40	6.00	6.00	6.00	4.40	3.00
cycles	4.40	4.40	3.00	3.00	6.00	4.40	4.40	6.00	6.00	6.00	4.40	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.00
Dispatch	6.00
Overall L1	11.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

INT

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.00 cycles. At this rate:

1% of peak load performance is reached (3.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402e50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x1c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x28(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4ceb87e20,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x401050,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
LEA -0x1c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0	0.50	0.50	0.50	0.50	0	0	0	2.14	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x28(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 402f7e <main.extracted.50+0x12e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %R8,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x334905060,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $0x19a685060,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $0x4030d0,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x405060,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND $0x7ffffffc,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
JE 402f46 <main.extracted.50+0xf6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%R8,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VBROADCASTSD (%R9),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RCX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 402f48 <main.extracted.50+0xf8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 402f7e <main.extracted.50+0x12e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SAL $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R9),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x4ceb87e40,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV $0x401030,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	1.75	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.50–	92.52	4.32
○Loop 16 - stream.c:355-356 - exec	92.52	4.21
○Loop 15 - stream.c:355-356 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code